ARM LDRT assembly parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index b6bfece..f8aee86 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -953,8 +953,8 @@
     case ARM::LDR_PRE:
     case ARM::LDRBT_POST_REG:
     case ARM::LDRBT_POST_IMM:
-    case ARM::LDRTr:
-    case ARM::LDRTi:
+    case ARM::LDRT_POST_REG:
+    case ARM::LDRT_POST_IMM:
       DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
       break;
     default: