commit 59fc42debd571bbafc52c20bc418fdc3f4d00188
author Daniel Dunbar <daniel@zuster.org> Tue Aug 11 20:59:47 2009 +0000
committer Daniel Dunbar <daniel@zuster.org> Tue Aug 11 20:59:47 2009 +0000
tree 185c53d1fab5944078b6ad9ed67f13f93f780f62
parent a942ad3d995fe153b2b905b3d57e285a57240514

llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be
used to strip hard coded comments out of .td assembly strings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78716 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/Target.td

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index dcbf5f2..d4a1850 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -484,6 +484,17 @@
   // used to support targets that need to parser multiple formats for the 
   // assembly language.
   int Variant = 0;
+
+  // CommentDelimiter - If given, the delimiter string used to recognize
+  // comments which are hard coded in the .td assembler strings for individual
+  // instructions.
+  string CommentDelimiter = "";
+
+  // RegisterPrefix - If given, the token prefix which indicates a register
+  // token. This is used by the matcher to automatically recognize hard coded
+  // register tokens as constrained registers, instead of tokens, for the
+  // purposes of matching.
+  string RegisterPrefix = "";
 }
 def DefaultAsmParser : AsmParser;
 

lib/Target/X86/X86.td

diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index effbddc..e7aa1f2 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -182,6 +182,12 @@
 def ATTAsmParser : AsmParser {
   string AsmParserClassName  = "ATTAsmParser";
   int Variant = 0;
+
+  // Discard comments in assembly strings.
+  string CommentDelimiter = "#";
+
+  // Recognize hard coded registers.
+  string RegisterPrefix = "%";
 }
 
 // The X86 target supports two different syntaxes for emitting machine code.

utils/TableGen/AsmMatcherEmitter.cpp

diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp
index 57b93b1..4dbd24c 100644
--- a/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/utils/TableGen/AsmMatcherEmitter.cpp
@@ -501,6 +501,15 @@
 
 class AsmMatcherInfo {
 public:
+  /// The tablegen AsmParser record.
+  Record *AsmParser;
+
+  /// The AsmParser "CommentDelimiter" value.
+  std::string CommentDelimiter;
+
+  /// The AsmParser "RegisterPrefix" value.
+  std::string RegisterPrefix;
+
   /// The classes which are needed for matching.
   std::vector<ClassInfo*> Classes;
   
@@ -537,6 +546,8 @@
   void BuildOperandClasses(CodeGenTarget &Target);
 
 public:
+  AsmMatcherInfo(Record *_AsmParser);
+
   /// BuildInfo - Construct the various tables used during matching.
   void BuildInfo(CodeGenTarget &Target);
 };
@@ -778,6 +789,13 @@
   }
 }
 
+AsmMatcherInfo::AsmMatcherInfo(Record *_AsmParser) 
+  : AsmParser(_AsmParser),
+    CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
+    RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
+{
+}
+
 void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
   // Build info for the register classes.
   BuildRegisterClasses(Target);
@@ -801,6 +819,13 @@
     II->Instr = &it->second;
     II->AsmString = FlattenVariants(CGI.AsmString, 0);
 
+    // Remove comments from the asm string.
+    if (!CommentDelimiter.empty()) {
+      size_t Idx = StringRef(II->AsmString).find(CommentDelimiter);
+      if (Idx != StringRef::npos)
+        II->AsmString = II->AsmString.substr(0, Idx);
+    }
+
     TokenizeAsmString(II->AsmString, II->Tokens);
 
     // Ignore instructions which shouldn't be matched.
@@ -1309,7 +1334,7 @@
   EmitMatchRegisterName(Target, AsmParser, OS);
 
   // Compute the information on the instructions to match.
-  AsmMatcherInfo Info;
+  AsmMatcherInfo Info(AsmParser);
   Info.BuildInfo(Target);
 
   // Sort the instruction table using the partial order on classes.