commit 5e9f35234653123de9b7b0bf4deb1012cd7deb63
author Tanya Lattner <tonic@nondot.org> Tue Mar 29 20:35:10 2005 +0000
committer Tanya Lattner <tonic@nondot.org> Tue Mar 29 20:35:10 2005 +0000
tree fd7fcd84e362a1900e0070dbfa16737df50adeed
parent 5ec3a63f6d3626a7ed278f72ac42119736c1af4e

Compare dependence analysis with llvm instructions versus machine instrutions. the  problem with using machine instructions and alias analysis is that aa does not handle tmp instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20931 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp

diff --git a/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp b/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp
index 5441d3c..6adb5f5 100644
--- a/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp
+++ b/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp
@@ -152,6 +152,7 @@
   //Get MachineFunction
   MachineFunction &MF = MachineFunction::get(&F);
  
+  DependenceAnalyzer &DA = getAnalysis<DependenceAnalyzer>();
   AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
   TargetData &TD = getAnalysis<TargetData>();
 
@@ -191,7 +192,7 @@
       continue;
     }
 
-    MSchedGraph *MSG = new MSchedGraph(*BI, target, AA, TD, indVarInstrs[*BI]);
+    MSchedGraph *MSG = new MSchedGraph(*BI, target, AA, TD, indVarInstrs[*BI], DA, machineTollvm[*BI]);
     
     //Write Graph out to file
     DEBUG(WriteGraphToFile(std::cerr, F.getName(), MSG));
@@ -349,7 +350,6 @@
   if(BI->getBasicBlock()->size() == 1)
     return false;
 
-
   //Increase number of single basic block loops for stats
   ++SingleBBLoops;
 
@@ -363,8 +363,11 @@
   for(MachineBasicBlock::const_iterator I = BI->begin(), E = BI->end(); I != E; ++I) {
     //Get opcode to check instruction type
     MachineOpCode OC = I->getOpcode();
+    
+    //Look for calls
     if(TMI->isCall(OC))
       return false;
+    
     //Look for conditional move
     if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi 
        || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
@@ -422,6 +425,15 @@
 	  std::cerr << **N << "\n";
 	});
 
+  //Create map of machine instr to llvm instr
+  std::map<MachineInstr*, Instruction*> mllvm;
+  for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
+    MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+    for (unsigned j = 0; j < tempMvec.size(); j++) {
+      mllvm[tempMvec[j]] = I;
+    }
+  }
+
   //Convert list of LLVM Instructions to list of Machine instructions
   std::map<const MachineInstr*, unsigned> mIndVar;
   for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
@@ -443,7 +455,7 @@
 
   //Put into a map for future access
   indVarInstrs[BI] = mIndVar;
-
+  machineTollvm[BI] = mllvm;
   return true;
 }
 
@@ -1864,7 +1876,7 @@
   MSchedGraphNode *branch = 0;
   MSchedGraphNode *BAbranch = 0;
 
-  schedule.print(std::cerr);
+  DEBUG(schedule.print(std::cerr));
 
   std::vector<MSchedGraphNode*> branches;