| commit | 6018deefe823598a3bbe03de9af354d269ae2130 | [log] [tgz] |
|---|---|---|
| author | Andrew Trick <atrick@apple.com> | Tue Jan 04 00:32:57 2011 +0000 |
| committer | Andrew Trick <atrick@apple.com> | Tue Jan 04 00:32:57 2011 +0000 |
| tree | 1514eb254ea72aa977b4f62e8cfacaf020c21c5c | |
| parent | a1cb585384f593517a9b8f48693f5e478b833fba [diff] [blame] |
Fix the ARM IIC_iCMPsi itinerary and add an important assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 6290e67..2b53cfd 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -240,6 +240,7 @@ // clear the lowest bit allStage1Units ^= allStage1Units & ~(allStage1Units - 1); } + assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); } bool ARMSubtarget::enablePostRAScheduler(