commit 640f299b44a35ed628a58f9c0c948067d629aa0c
author Evan Cheng <evan.cheng@apple.com> Thu Dec 01 00:43:55 2005 +0000
committer Evan Cheng <evan.cheng@apple.com> Thu Dec 01 00:43:55 2005 +0000
tree 311fb56b68a7bc5e2075cd051b114e22a792561b
parent c121e33e35b2e7292e6d99d8db91f73b84269e36

Proper support for shifts with register shift value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24559 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelDAGToDAG.cpp

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 27db21e..59f659a 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -134,10 +134,11 @@
 void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode &AM) {
   MatchAddress(N, AM);
 
-  if (AM.BaseType == X86ISelAddressMode::RegBase && !AM.Base.Reg.Val) {
-    AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
-  } else {
-    AM.Base.Reg = Select(AM.Base.Reg);
+  if (AM.BaseType == X86ISelAddressMode::RegBase) {
+    if (AM.Base.Reg.Val)
+      AM.Base.Reg = Select(AM.Base.Reg);
+    else
+      AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
   }
   if (!AM.IndexReg.Val) {
     AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
@@ -277,10 +278,8 @@
     default: break;
 
     case ISD::SHL:
-    case ISD::SRL:
-    case ISD::SRA:
       if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
-        if (N->getOpcode() == ISD::SHL && CN->getValue() == 1) {
+        if (CN->getValue() == 1) {
           // X = SHL Y, 1  -> X = ADD Y, Y
           switch (OpVT) {
             default: assert(0 && "Cannot shift this type!");
@@ -291,34 +290,6 @@
           SDOperand Tmp0 = Select(N->getOperand(0));
           return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
         }
-      } else {
-        static const unsigned SHLTab[] = {
-          X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL
-        };
-        static const unsigned SRLTab[] = {
-          X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL
-        };
-        static const unsigned SRATab[] = {
-          X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL
-        };
-
-        switch (OpVT) {
-          default: assert(0 && "Cannot shift this type!");
-          case MVT::i1:
-          case MVT::i8:  Opc = 0; break;
-          case MVT::i16: Opc = 1; break;
-          case MVT::i32: Opc = 2; break;
-        }
-
-        switch (N->getOpcode()) {
-          default: assert(0 && "Unreachable!");
-          case ISD::SHL: Opc = SHLTab[Opc]; break;
-          case ISD::SRL: Opc = SRLTab[Opc]; break;
-          case ISD::SRA: Opc = SRATab[Opc]; break;
-        }
-
-        SDOperand Tmp0 = Select(N->getOperand(0));
-        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
       }
       break;