commit 64d80e3387f328d21cd9cc06464b5de7861e3f27
author Evan Cheng <evan.cheng@apple.com> Thu Jul 19 01:14:50 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Thu Jul 19 01:14:50 2007 +0000
tree 203a9dfb41eba2fd8bd65a1e8bb80f73e36c0771
parent 4558b807a2076e199bcb019f5edc9eabbc5922c1

Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaInstrFormats.td

diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td
index 259e9af..1d430f2 100644
--- a/lib/Target/Alpha/AlphaInstrFormats.td
+++ b/lib/Target/Alpha/AlphaInstrFormats.td
@@ -57,7 +57,8 @@
         : InstAlpha<opcode, asmstr, itin> {    
   bits<5> Ra;
 
-  let OperandList = (ops GPRC:$RA);
+  let OutOperandList = (ops GPRC:$RA);
+  let InOperandList = (ops);
   let Inst{25-21} = Ra;
   let Inst{20-16} = 0;
   let Inst{15-0} = fc;
@@ -69,7 +70,8 @@
   bits<5> Rb;
   bits<14> disp;
 
-  let OperandList = OL;
+  let OutOperandList = (ops);
+  let InOperandList = OL;
 
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
@@ -83,7 +85,8 @@
   bits<5> Rb;
   bits<14> disp;
 
-  let OperandList = OL;
+  let OutOperandList = (ops);
+  let InOperandList = OL;
 
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
@@ -97,7 +100,8 @@
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
 class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
    : InstAlpha<opcode, asmstr, itin> {
-  let OperandList = OL;
+  let OutOperandList = (ops);
+  let InOperandList = OL;
   bits<64> Opc; //dummy
   bits<5> Ra;
   bits<21> disp;
@@ -111,7 +115,8 @@
 class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops target:$DISP);
+  let OutOperandList = (ops);
+  let InOperandList = (ops target:$DISP);
   bits<5> Ra;
   bits<21> disp;
 
@@ -123,7 +128,8 @@
 class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RC, GPRC:$RA, GPRC:$RB);
+  let OutOperandList = (outs GPRC:$RC);
+  let InOperandList = (ins GPRC:$RA, GPRC:$RB);
 
   bits<5> Rc;
   bits<5> Ra;
@@ -141,7 +147,8 @@
 class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RC, GPRC:$RB);
+  let OutOperandList = (outs GPRC:$RC);
+  let InOperandList = (ins GPRC:$RB);
 
   bits<5> Rc;
   bits<5> Rb;
@@ -158,7 +165,8 @@
 class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RDEST, GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
+  let OutOperandList = (outs GPRC:$RDEST);
+  let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
   let Constraints = "$RFALSE = $RDEST";
   let DisableEncoding = "$RFALSE";
 
@@ -180,7 +188,8 @@
 class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RC, GPRC:$RA, u8imm:$L);
+  let OutOperandList = (outs GPRC:$RC);
+  let InOperandList = (ins GPRC:$RA, u8imm:$L);
 
   bits<5> Rc;
   bits<5> Ra;
@@ -197,7 +206,8 @@
 class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RDEST, GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
+  let OutOperandList = (outs GPRC:$RDEST);
+  let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
   let Constraints = "$RFALSE = $RDEST";
   let DisableEncoding = "$RFALSE";
 
@@ -233,7 +243,8 @@
 //3.3.5
 class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
     : InstAlpha<opcode, asmstr, itin> {
-  let OperandList = OL;
+  let OutOperandList = (ops);
+  let InOperandList = OL;
   bits<26> Function;
 
   let Inst{25-0} = Function;
@@ -241,9 +252,10 @@
 
 
 // Pseudo instructions.
-class PseudoInstAlpha<dag OL, string nm, list<dag> pattern, InstrItinClass itin> 
+class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<0, nm, itin>  {
-  let OperandList = OL;
+  let OutOperandList = OOL;
+  let InOperandList = IOL;
   let Pattern = pattern;
 
 }