Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 54c7101..8312d14 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -62,8 +62,8 @@
abort();
case 1:
return SDOperand(); // ret void is legal
- case 2:
- Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
+ case 3:
+ Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
break;
}
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 837a911..0073bea 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -231,7 +231,7 @@
Select(Chain, N->getOperand(0)); // Token chain.
SDOperand InFlag(0,0);
- if (N->getNumOperands() == 2) {
+ if (N->getNumOperands() == 3) {
SDOperand Val;
Select(Val, N->getOperand(1));
if (N->getOperand(1).getValueType() == MVT::i64) {
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 9de5447..6c81458 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -562,7 +562,7 @@
AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
AR_PFSVal);
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
- case 2: {
+ case 3: {
// Copy the result into the output register & restore ar.pfs
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index b33aeb8..18e1cba 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1160,7 +1160,7 @@
abort();
case 1:
return SDOperand(); // ret void is legal
- case 2: {
+ case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
if (MVT::isVector(ArgVT))
@@ -1180,8 +1180,8 @@
DAG.getMachineFunction().addLiveOut(ArgReg);
break;
}
- case 3:
- Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
+ case 5:
+ Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
// If we haven't noted the R3+R4 are live out, do so now.
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index b5eafaa..ca91dc1 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -857,7 +857,7 @@
abort();
case 1:
return SDOperand(); // ret void is legal
- case 2: {
+ case 3: {
unsigned ArgReg;
switch(Op.getOperand(1).getValueType()) {
default: assert(0 && "Unknown type to return!");
@@ -869,8 +869,8 @@
SDOperand());
break;
}
- case 3:
- Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
+ case 5:
+ Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
break;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1d2f6e4..4aaf991 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3326,7 +3326,7 @@
case 1: // ret void.
return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
- case 2: {
+ case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
if (MVT::isVector(ArgVT)) {
@@ -3394,13 +3394,13 @@
}
break;
}
- case 3:
+ case 5:
if (DAG.getMachineFunction().liveout_empty()) {
DAG.getMachineFunction().addLiveOut(X86::EAX);
DAG.getMachineFunction().addLiveOut(X86::EDX);
}
- Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
+ Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
break;