Adjust to CopyFromReg changes, implement deletion of truncating/extending
stores/loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19562 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index e47bb59..4f7c0a8 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -239,11 +239,16 @@
case ISD::FrameIndex:
case ISD::GlobalAddress:
case ISD::ExternalSymbol:
- case ISD::ConstantPool:
- case ISD::CopyFromReg: // Nothing to do.
+ case ISD::ConstantPool: // Nothing to do.
assert(getTypeAction(Node->getValueType(0)) == Legal &&
"This must be legal!");
break;
+ case ISD::CopyFromReg:
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ if (Tmp1 != Node->getOperand(0))
+ Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(),
+ Node->getValueType(0), Tmp1);
+ break;
case ISD::ImplicitDef:
Tmp1 = LegalizeOp(Node->getOperand(0));
if (Tmp1 != Node->getOperand(0))
@@ -752,8 +757,12 @@
case ISD::CopyFromReg: {
unsigned Reg = cast<RegSDNode>(Node)->getReg();
// Aggregate register values are always in consequtive pairs.
- Lo = DAG.getCopyFromReg(Reg, NVT);
- Hi = DAG.getCopyFromReg(Reg+1, NVT);
+ Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
+ Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
+
+ // Remember that we legalized the chain.
+ AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
+
assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
break;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 86a0120..e1b5201 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -220,6 +220,29 @@
N->getOperand(1)),
cast<SetCCSDNode>(N)->getCondition()));
break;
+ case ISD::TRUNCSTORE: {
+ EVTStruct NN;
+ NN.Opcode = ISD::TRUNCSTORE;
+ NN.VT = N->getValueType(0);
+ NN.EVT = cast<MVTSDNode>(N)->getExtraValueType();
+ NN.Ops.push_back(N->getOperand(0));
+ NN.Ops.push_back(N->getOperand(1));
+ NN.Ops.push_back(N->getOperand(2));
+ MVTSDNodes.erase(NN);
+ break;
+ }
+ case ISD::EXTLOAD:
+ case ISD::SEXTLOAD:
+ case ISD::ZEXTLOAD: {
+ EVTStruct NN;
+ NN.Opcode = N->getOpcode();
+ NN.VT = N->getValueType(0);
+ NN.EVT = cast<MVTSDNode>(N)->getExtraValueType();
+ NN.Ops.push_back(N->getOperand(0));
+ NN.Ops.push_back(N->getOperand(1));
+ MVTSDNodes.erase(NN);
+ break;
+ }
default:
if (N->getNumOperands() == 1)
UnaryOps.erase(std::make_pair(N->getOpcode(),
@@ -861,7 +884,7 @@
SDNode *&N = MVTSDNodes[NN];
if (N) return SDOperand(N, 0);
- N = new MVTSDNode(Opcode, VT, N1, N2, EVT);
+ N = new MVTSDNode(Opcode, VT, MVT::Other, N1, N2, EVT);
AllNodes.push_back(N);
return SDOperand(N, 0);
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index ed363e1..2d264c0 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -254,7 +254,7 @@
std::map<const Value*, unsigned>::const_iterator VMI =
FuncInfo.ValueMap.find(V);
assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
- return N = DAG.getCopyFromReg(VMI->second, VT);
+ return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
}
const SDOperand &setValue(const Value *V, SDOperand NewN) {