Allow itineraries to be passed through the Target Machine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 9eb1f67..0ec7803 100644
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -178,8 +178,8 @@
 // CollectAllItinClasses - Gathers and enumerates all the itinerary classes.
 // Returns itinerary class count.
 //
-unsigned SubtargetEmitter::CollectAllItinClasses(std::map<std::string, unsigned>
-                                                              &ItinClassesMap) {
+unsigned SubtargetEmitter::CollectAllItinClasses(std::ostream &OS,
+                              std::map<std::string, unsigned> &ItinClassesMap) {
   // Gather and sort all itinerary classes
   std::vector<Record*> ItinClassList =
                             Records.getAllDerivedDefinitions("InstrItinClass");
@@ -196,6 +196,11 @@
     ItinClassesMap[Name] = i;
   }
   
+  // Emit size of table
+  OS<<"\nenum {\n";
+  OS<<"  ItinClassesSize = " << N << "\n";
+  OS<<"};\n";
+
   // Return itinerary class count
   return N;
 }
@@ -313,6 +318,11 @@
   
   // End stages table
   OS << "};\n";
+  
+  // Emit size of table
+  OS<<"\nenum {\n";
+  OS<<"  StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n";
+  OS<<"};\n";
 }
 
 //
@@ -421,13 +431,18 @@
   std::vector<std::vector<InstrItinerary> > ProcList;
   
   // Enumerate all the itinerary classes
-  unsigned NItinClasses = CollectAllItinClasses(ItinClassesMap);
-  // Emit the stage data
-  EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
-  // Emit the processor itinerary data
-  EmitProcessorData(OS, ProcList);
-  // Emit the processor lookup data
-  EmitProcessorLookup(OS);
+  unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap);
+  // Make sure the rest is worth the effort
+  HasItineraries = NItinClasses != 0;
+  
+  if (HasItineraries) {
+    // Emit the stage data
+    EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
+    // Emit the processor itinerary data
+    EmitProcessorData(OS, ProcList);
+    // Emit the processor lookup data
+    EmitProcessorLookup(OS);
+  }
 }
 
 //
@@ -460,9 +475,15 @@
     
     OS << "  " << Attribute << " = (Bits & " << Instance << ") != 0;\n";
   }
-  OS << "\n"
-     << "  InstrItinerary *Itin = (InstrItinerary *)"
-                        "Features.getInfo(SubTypeInfoKV, SubTypeInfoKVSize);\n";
+  
+  if (HasItineraries) {
+    OS << "\n"
+       << "  InstrItinerary *Itinerary = (InstrItinerary *)"
+                        "Features.getInfo(SubTypeInfoKV, SubTypeInfoKVSize);\n"
+          "  InstrItins = InstrItineraryData(Stages, StagesSize, "
+                                             "Itinerary, ItinClassesSize);\n";
+  }
+  
   OS << "}\n";
 }