| commit | 6de3c6f1a926f49cca2fd207ab4eeb6c35e0e068 | [log] [tgz] |
|---|---|---|
| author | Owen Anderson <resistor@mac.com> | Wed Sep 07 17:55:19 2011 +0000 |
| committer | Owen Anderson <resistor@mac.com> | Wed Sep 07 17:55:19 2011 +0000 |
| tree | 99f17aa5337fe5488b9c8d7f87ee7b0529e4cbd3 | |
| parent | b950585cc5a0d665e9accfe5ce490cd269756f2e [diff] [blame] |
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index cd0e5e4..3b4e1c5 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2786,7 +2786,7 @@ break; case 0xf3bf8f6: Inst.setOpcode(ARM::t2ISB); - return MCDisassembler::Success; + break; } unsigned imm = fieldFromInstruction32(Insn, 0, 4);