commit 6e438701fb95c729ae10e42a3faeffba3f70810c
author Dan Gohman <gohman@apple.com> Mon Apr 27 16:33:14 2009 +0000
committer Dan Gohman <gohman@apple.com> Mon Apr 27 16:33:14 2009 +0000
tree 055f50bed9e7d9e11491f4d1cf65235b1a49ff35
parent 70a8a1122a6f9f06767a6ab139b310e3fd5aaccd

Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index d8c0833..e748e11 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1681,13 +1681,13 @@
         Opc = X86::MOV8rr_NOREX;
       else
         Opc = X86::MOV8rr;
-    } else if (CommonRC == &X86::GR64_RegClass) {
+    } else if (CommonRC == &X86::GR64_ABCDRegClass) {
       Opc = X86::MOV64rr;
-    } else if (CommonRC == &X86::GR32_RegClass) {
+    } else if (CommonRC == &X86::GR32_ABCDRegClass) {
       Opc = X86::MOV32rr;
-    } else if (CommonRC == &X86::GR16_RegClass) {
+    } else if (CommonRC == &X86::GR16_ABCDRegClass) {
       Opc = X86::MOV16rr;
-    } else if (CommonRC == &X86::GR8_RegClass) {
+    } else if (CommonRC == &X86::GR8_ABCDRegClass) {
       Opc = X86::MOV8rr;
     } else if (CommonRC == &X86::GR64_NOREXRegClass) {
       Opc = X86::MOV64rr;
@@ -1802,13 +1802,13 @@
     Opc = X86::MOV16mr;
   } else if (RC == &X86::GR8RegClass) {
     Opc = X86::MOV8mr;
-  } else if (RC == &X86::GR64_RegClass) {
+  } else if (RC == &X86::GR64_ABCDRegClass) {
     Opc = X86::MOV64mr;
-  } else if (RC == &X86::GR32_RegClass) {
+  } else if (RC == &X86::GR32_ABCDRegClass) {
     Opc = X86::MOV32mr;
-  } else if (RC == &X86::GR16_RegClass) {
+  } else if (RC == &X86::GR16_ABCDRegClass) {
     Opc = X86::MOV16mr;
-  } else if (RC == &X86::GR8_RegClass) {
+  } else if (RC == &X86::GR8_ABCDRegClass) {
     Opc = X86::MOV8mr;
   } else if (RC == &X86::GR64_NOREXRegClass) {
     Opc = X86::MOV64mr;
@@ -1882,13 +1882,13 @@
     Opc = X86::MOV16rm;
   } else if (RC == &X86::GR8RegClass) {
     Opc = X86::MOV8rm;
-  } else if (RC == &X86::GR64_RegClass) {
+  } else if (RC == &X86::GR64_ABCDRegClass) {
     Opc = X86::MOV64rm;
-  } else if (RC == &X86::GR32_RegClass) {
+  } else if (RC == &X86::GR32_ABCDRegClass) {
     Opc = X86::MOV32rm;
-  } else if (RC == &X86::GR16_RegClass) {
+  } else if (RC == &X86::GR16_ABCDRegClass) {
     Opc = X86::MOV16rm;
-  } else if (RC == &X86::GR8_RegClass) {
+  } else if (RC == &X86::GR8_ABCDRegClass) {
     Opc = X86::MOV8rm;
   } else if (RC == &X86::GR64_NOREXRegClass) {
     Opc = X86::MOV64rm;