Codegen x < 0 | y < 0 as (x|y) < 0. This allows us to compile this to:
_foo:
or r2, r4, r3
srwi r3, r2, 31
blr
instead of:
_foo:
srwi r2, r4, 31
srwi r3, r3, 31
or r3, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21544 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2eccb6b..10b6b76 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -809,6 +809,7 @@
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
+ // TODO we could handle some SRA cases here.
default: break;
}
@@ -1061,11 +1062,13 @@
// (X != 0) | (Y != 0) -> (X|Y != 0)
// (X == 0) & (Y == 0) -> (X|Y == 0)
+ // (X < 0) | (Y < 0) -> (X|Y < 0)
if (LR == RR && isa<ConstantSDNode>(LR) &&
cast<ConstantSDNode>(LR)->getValue() == 0 &&
Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) {
if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) ||
- (Op2 == ISD::SETNE && Opcode == ISD::OR))
+ (Op2 == ISD::SETNE && Opcode == ISD::OR) ||
+ (Op2 == ISD::SETLT && Opcode == ISD::OR))
return getSetCC(Op2, VT,
getNode(ISD::OR, LR.getValueType(), LL, RL), LR);
}