| commit | 6f73af9a8766a04293ed23e20138380f73f42bb0 | [log] [tgz] |
|---|---|---|
| author | Anton Korobeynikov <asl@math.spbu.ru> | Thu Jul 16 13:44:30 2009 +0000 |
| committer | Anton Korobeynikov <asl@math.spbu.ru> | Thu Jul 16 13:44:30 2009 +0000 |
| tree | cc11a545b86390f1ad292880f4d8c96aa5678e14 | |
| parent | 87b83aa61572ea03976ddcb8ce57702aebce58eb [diff] [blame] |
Add patterns for various extloads git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index e379c69..83fea60 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -221,6 +221,9 @@ if (Depth > 5) return MatchAddressBase(N, AM); + // FIXME: We can perform better here. If we have something like + // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of + // imm into addressing mode. switch (N.getOpcode()) { default: break; case ISD::Constant: {