rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index bd66159..250298e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -51,7 +51,7 @@
unsigned ResNo = Use->getOperand(2).ResNo;
if (Def->isTargetOpcode()) {
- const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
+ const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
if (ResNo >= II.getNumDefs() &&
II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
@@ -148,7 +148,7 @@
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
@@ -291,15 +291,15 @@
static const TargetRegisterClass *getInstrOperandRegClass(
const MRegisterInfo *MRI,
const TargetInstrInfo *TII,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc &II,
unsigned Op) {
- if (Op >= II->getNumOperands()) {
- assert(II->isVariadic() && "Invalid operand # of instruction");
+ if (Op >= II.getNumOperands()) {
+ assert(II.isVariadic() && "Invalid operand # of instruction");
return NULL;
}
- if (II->OpInfo[Op].isLookupPtrRegClass())
+ if (II.OpInfo[Op].isLookupPtrRegClass())
return TII->getPointerRegClass();
- return MRI->getRegClass(II->OpInfo[Op].RegClass);
+ return MRI->getRegClass(II.OpInfo[Op].RegClass);
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
@@ -371,7 +371,7 @@
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
MachineInstr *MI,
- const TargetInstrDescriptor &II,
+ const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// If the specific node value is only used by a CopyToReg and the dest reg
@@ -396,7 +396,7 @@
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
assert(RC && "Isn't a register operand!");
VRBase = RegInfo.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
@@ -422,7 +422,7 @@
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
@@ -434,16 +434,16 @@
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- const TargetInstrDescriptor *TID = MI->getDesc();
- bool isOptDef = (IIOpNum < TID->getNumOperands())
- ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ bool isOptDef = (IIOpNum < TID.getNumOperands())
+ ? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
@@ -507,7 +507,7 @@
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
@@ -669,7 +669,7 @@
return;
}
- const TargetInstrDescriptor &II = TII->get(Opc);
+ const TargetInstrDesc &II = TII->get(Opc);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 8096596..4cd4577 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -148,7 +148,7 @@
if (!SU || !SU->Node) continue;
if (SU->isCommutable) {
unsigned Opc = SU->Node->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = CountOperands(SU->Node);
for (unsigned j = 0; j != NumOps; ++j) {
@@ -431,7 +431,7 @@
SUnit *NewSU = NewSUnit(N);
SUnitMap[N].push_back(NewSU);
- const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
@@ -622,7 +622,7 @@
/// FIXME: Move to SelectionDAG?
static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
- const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
unsigned NumRes = TID.getNumDefs();
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
@@ -665,7 +665,7 @@
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
if (!Node || !Node->isTargetOpcode())
continue;
- const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
if (!TID.ImplicitDefs)
continue;
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
@@ -1288,7 +1288,7 @@
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
if (SU->isTwoAddress) {
unsigned Opc = SU->Node->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
for (unsigned i = 0; i != NumOps; ++i) {
@@ -1364,7 +1364,7 @@
continue;
unsigned Opc = Node->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(Node);
for (unsigned j = 0; j != NumOps; ++j) {