rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 8896b35..85c1048 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -175,7 +175,7 @@
   // If there is only one terminator instruction, process it.
   unsigned LastOpc = LastInst->getOpcode();
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
-    if (!LastInst->getDesc()->isBranch())
+    if (!LastInst->getDesc().isBranch())
       return true;
 
     // Unconditional branch
@@ -259,7 +259,7 @@
     } else {
       // Conditional branch.
       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
-      const TargetInstrDescriptor &TID = get(Opc);
+      const TargetInstrDesc &TID = get(Opc);
 
       if (TID.getNumOperands() == 3)
         BuildMI(&MBB, TID).addReg(Cond[1].getReg())
@@ -275,15 +275,13 @@
   
   // Two-way Conditional branch.
   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
-  const TargetInstrDescriptor &TID = get(Opc);
+  const TargetInstrDesc &TID = get(Opc);
 
   if (TID.getNumOperands() == 3)
-    BuildMI(&MBB, TID).addReg(Cond[1].getReg())
-                      .addReg(Cond[2].getReg())
+    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
                       .addMBB(TBB);
   else
-    BuildMI(&MBB, TID).addReg(Cond[1].getReg())
-                      .addMBB(TBB);
+    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
 
   BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
   return 2;