commit 78268b943669cd0c0e1e874e2a329fcf200bd59b
author Evan Cheng <evan.cheng@apple.com> Mon Jan 29 22:22:24 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jan 29 22:22:24 2007 +0000
tree 7a213f94fc0d4062364a45291be9312b0f9379c0
parent 1620f1ad914bc6039f5d6c04ef4234f5bef30d20

Remember if LR register has been spilled in this function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33632 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMMachineFunctionInfo.h

diff --git a/lib/Target/ARM/ARMMachineFunctionInfo.h b/lib/Target/ARM/ARMMachineFunctionInfo.h
index 05dc0dc..6ce4d53 100644
--- a/lib/Target/ARM/ARMMachineFunctionInfo.h
+++ b/lib/Target/ARM/ARMMachineFunctionInfo.h
@@ -36,6 +36,10 @@
   /// processFunctionBeforeCalleeSavedScan().
   bool HasStackFrame;
 
+  /// LRSpilled - True if the LR register has been spilled.
+  ///
+  bool LRSpilled;
+
   /// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer
   /// spill stack offset.
   unsigned FramePtrSpillOffset;
@@ -71,14 +75,14 @@
 public:
   ARMFunctionInfo() :
     isThumb(false),
-    VarArgsRegSaveSize(0), HasStackFrame(false), FramePtrSpillOffset(0),
-    GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
+    VarArgsRegSaveSize(0), HasStackFrame(false), LRSpilled(false),
+    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
     GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), JumpTableUId(0) {}
 
   ARMFunctionInfo(MachineFunction &MF) :
     isThumb(MF.getTarget().getSubtarget<ARMSubtarget>().isThumb()),
-    VarArgsRegSaveSize(0), HasStackFrame(false), FramePtrSpillOffset(0),
-    GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
+    VarArgsRegSaveSize(0), HasStackFrame(false), LRSpilled(false),
+    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
     GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), JumpTableUId(0) {}
 
   bool isThumbFunction() const { return isThumb; }
@@ -88,6 +92,10 @@
 
   bool hasStackFrame() const { return HasStackFrame; }
   void setHasStackFrame(bool s) { HasStackFrame = s; }
+
+  bool isLRSpilled() const { return LRSpilled; }
+  void setLRIsSpilled(bool s) { LRSpilled = s; }
+
   unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; }
   void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; }
   

lib/Target/ARM/ARMRegisterInfo.cpp

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 912d17a..2accaf8 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -769,13 +769,14 @@
     }
   }
 
+  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   if (!CanEliminateFrame) {
-    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     AFI->setHasStackFrame(true);
 
     // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
     // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
     if (!LRSpilled && CS1Spilled) {
+      LRSpilled = true;
       MF.changePhyRegUsed(ARM::LR, true);
       NumGPRSpills++;
       UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
@@ -798,6 +799,9 @@
         MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true);
     }
   }
+
+  // Remembe if LR has been spilled.
+  AFI->setLRIsSpilled(LRSpilled);
 }
 
 /// Move iterator pass the next bunch of callee save load / store ops for