If val# def is ~0U, meaning it's defined by a PHI, and it's previously split, spill before the barrier because it's impossible to determine if all the defs are spilled in the same spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58129 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/PreAllocSplitting.cpp b/lib/CodeGen/PreAllocSplitting.cpp
index 18cac07..1b2b635 100644
--- a/lib/CodeGen/PreAllocSplitting.cpp
+++ b/lib/CodeGen/PreAllocSplitting.cpp
@@ -527,21 +527,23 @@
int SS;
unsigned SpillIndex = 0;
MachineInstr *SpillMI = NULL;
- if (isAlreadySplit(CurrLI->reg, ValNo->id, SS)) {
- // If it's already split, just restore the value. There is no need to spill
- // the def again.
- } else if (ValNo->def == ~0U) {
+ bool PrevSpilled = isAlreadySplit(CurrLI->reg, ValNo->id, SS);
+ if (ValNo->def == ~0U) {
// If it's defined by a phi, we must split just before the barrier.
MachineBasicBlock::iterator SpillPt =
findSpillPoint(BarrierMBB, Barrier, RefsInMBB, SpillIndex);
if (SpillPt == BarrierMBB->begin())
return false; // No gap to insert spill.
// Add spill.
- SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
+ if (!PrevSpilled)
+ // If previously split, reuse the spill slot.
+ SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
SpillMI = prior(SpillPt);
LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
- } else {
+ } else if (!PrevSpilled) {
+ // If it's already split, just restore the value. There is no need to spill
+ // the def again.
// Check if it's possible to insert a spill after the def MI.
MachineBasicBlock::iterator SpillPt =
findNextEmptySlot(DefMBB, DefMI, SpillIndex);
@@ -549,8 +551,8 @@
return false; // No gap to insert spill.
SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
- // Add spill. The store instruction kills the register if def is before the
- // barrier in the barrier block.
+ // Add spill. The store instruction kills the register if def is before
+ // the barrier in the barrier block.
TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
DefMBB == BarrierMBB, SS, RC);
SpillMI = prior(SpillPt);
@@ -567,7 +569,7 @@
// If live interval is spilled in the same block as the barrier, just
// create a hole in the interval.
if (!DefMBB ||
- (SpillIndex && SpillMI->getParent() == BarrierMBB)) {
+ (SpillMI && SpillMI->getParent() == BarrierMBB)) {
UpdateIntervalForSplit(ValNo, LIs->getUseIndex(SpillIndex)+1,
LIs->getDefIndex(RestoreIndex));