Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55349 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp
index 7864431..c9978e5 100644
--- a/utils/TableGen/FastISelEmitter.cpp
+++ b/utils/TableGen/FastISelEmitter.cpp
@@ -62,14 +62,15 @@
///
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
- MVT::SimpleValueType VT,
- const CodeGenRegisterClass *DstRC) {
+ MVT::SimpleValueType VT) {
if (!InstPatNode->isLeaf() &&
InstPatNode->getOperator()->getName() == "imm") {
Operands.push_back("i");
return true;
}
+ const CodeGenRegisterClass *DstRC = 0;
+
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
// For now, filter out any operand with a predicate.
@@ -105,8 +106,11 @@
if (!RC)
return false;
// For now, all the operands must have the same register class.
- if (DstRC != RC)
- return false;
+ if (DstRC) {
+ if (DstRC != RC)
+ return false;
+ } else
+ DstRC = RC;
Operands.push_back("r");
}
return true;
@@ -220,7 +224,10 @@
Record *InstPatOp = InstPatNode->getOperator();
std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
- MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
+ MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
+ MVT::SimpleValueType VT = RetVT;
+ if (InstPatNode->getNumChildren())
+ VT = InstPatNode->getChild(0)->getTypeNum(0);
// For now, filter out instructions which just set a register to
// an Operand or an immediate, like MOV32ri.
@@ -233,7 +240,7 @@
// Check all the operands.
OperandsSignature Operands;
- if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
+ if (!Operands.initialize(InstPatNode, Target, VT))
continue;
// Get the predicate that guards this pattern.
@@ -244,9 +251,9 @@
Pattern.getDstPattern()->getOperator()->getName(),
DstRC
};
- assert(!SimplePatterns[Operands][OpcodeName][VT][VT].count(PredicateCheck) &&
+ assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
"Duplicate pattern!");
- SimplePatterns[Operands][OpcodeName][VT][VT][PredicateCheck] = Memo;
+ SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
}
// Declare the target FastISel class.
@@ -398,7 +405,7 @@
// Emit one function for the type that demultiplexes on return type.
OS << "unsigned FastISel::FastEmit_"
<< getLegalCName(Opcode) << "_"
- << getLegalCName(getName(VT));
+ << getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
OS << "(MVT::SimpleValueType RetVT";
if (!Operands.empty())