commit 7c64fe651ad4581ac66b6407116144442a8a7f03
author Devang Patel <dpatel@apple.com> Mon Jan 23 18:31:58 2012 +0000
committer Devang Patel <dpatel@apple.com> Mon Jan 23 18:31:58 2012 +0000
tree fec6887f84c9db0c5acca483f8e2dc78f65dc724
parent 9df0fb4e8176325d713ba4eb67791e36cb833432

Intel syntax: Parse segment registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/AsmParser/X86AsmParser.cpp

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index a47e24a..f2fee36 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -54,7 +54,7 @@
   X86Operand *ParseATTOperand();
   X86Operand *ParseIntelOperand();
   X86Operand *ParseIntelMemOperand();
-  X86Operand *ParseIntelBracExpression(unsigned Size);
+  X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
   X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
 
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
@@ -593,8 +593,9 @@
   return Size;
 }
 
-X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
-  unsigned SegReg = 0, BaseReg = 0, IndexReg = 0, Scale = 1;
+X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
+                                                   unsigned Size) {
+  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
   SMLoc Start = Parser.getTok().getLoc(), End;
 
   const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
@@ -669,6 +670,7 @@
 X86Operand *X86AsmParser::ParseIntelMemOperand() {
   const AsmToken &Tok = Parser.getTok();
   SMLoc Start = Parser.getTok().getLoc(), End;
+  unsigned SegReg = 0;
 
   unsigned Size = getIntelMemOperandSize(Tok.getString());
   if (Size) {
@@ -678,7 +680,17 @@
   }
 
   if (getLexer().is(AsmToken::LBrac))
-    return ParseIntelBracExpression(Size);
+    return ParseIntelBracExpression(SegReg, Size);
+
+  if (!ParseRegister(SegReg, Start, End)) {
+    // Handel SegReg : [ ... ]
+    if (getLexer().isNot(AsmToken::Colon))
+      return ErrorOperand(Start, "Expected ':' token!");
+    Parser.Lex(); // Eat :
+    if (getLexer().isNot(AsmToken::LBrac))
+      return ErrorOperand(Start, "Expected '[' token!");
+    return ParseIntelBracExpression(SegReg, Size);
+  }
 
   const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
   if (getParser().ParseExpression(Disp, End)) return 0;