commit 7cbeb2431c7264d0848d1343f43914f970828ac7
author Chris Lattner <sabre@nondot.org> Thu Feb 21 04:55:52 2008 +0000
committer Chris Lattner <sabre@nondot.org> Thu Feb 21 04:55:52 2008 +0000
tree ecadd35d333d99053d8c8191802004f74ad77b8b
parent db71d63467bdb7b629641fee3272b47bd028e09f

Fix a (harmless) but where vregs were added to the used reg lists for 
inline asms.

Fix PR2078 by marking aliases of registers used when a register is 
marked used.  This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47426 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b5e39a1..f36a120 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3347,12 +3347,29 @@
   /// busy in OutputRegs/InputRegs.
   void MarkAllocatedRegs(bool isOutReg, bool isInReg,
                          std::set<unsigned> &OutputRegs, 
-                         std::set<unsigned> &InputRegs) const {
-     if (isOutReg)
-       OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
-     if (isInReg)
-       InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
-   }
+                         std::set<unsigned> &InputRegs,
+                         const TargetRegisterInfo &TRI) const {
+    if (isOutReg) {
+      for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
+        MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
+    }
+    if (isInReg) {
+      for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
+        MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
+    }
+  }
+  
+private:
+  /// MarkRegAndAliases - Mark the specified register and all aliases in the
+  /// specified set.
+  static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 
+                                const TargetRegisterInfo &TRI) {
+    assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
+    Regs.insert(Reg);
+    if (const unsigned *Aliases = TRI.getAliasSet(Reg))
+      for (; *Aliases; ++Aliases)
+        Regs.insert(*Aliases);
+  }
 };
 } // end anon namespace.
 
@@ -3491,7 +3508,8 @@
       }
     }
     OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
-    OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
+    const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
+    OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
     return;
   }
   
@@ -3519,7 +3537,6 @@
         Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
       
       OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
-      OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
       return;
     }
     
@@ -3571,7 +3588,7 @@
       
       OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 
                                          OpInfo.ConstraintVT);
-      OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
+      OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
       return;
     }
   }