partial implementation of the ARM Addressing Mode 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 9a19497..353e3fc 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -386,7 +386,7 @@
SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
- return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp);
+ return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
}
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
@@ -445,6 +445,7 @@
SDNode *Select(SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
+ bool SelectAddrMode1(SDOperand N, SDOperand &Arg);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@@ -478,6 +479,24 @@
return isInt12Immediate(Op.Val, Imm);
}
+bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
+ SDOperand &Arg) {
+ switch(N.getOpcode()) {
+ case ISD::CopyFromReg:
+ Arg = N;
+ return true;
+ case ISD::Constant: {
+ //TODO:check that we have a valid constant
+ int32_t t = cast<ConstantSDNode>(N)->getValue();
+ Arg = CurDAG->getTargetConstant(t, MVT::i32);
+ return true;
+ }
+ default:
+ std::cerr << "OpCode = " << N.getOpcode() << "\n";
+ assert(0);
+ }
+}
+
//register plus/minus 12 bit offset
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
SDOperand &Base) {