X86 lowers SELECT to a cmp / test followed by a conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24754 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 292f00a..1facdd3 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -113,6 +113,11 @@
// These should be promoted to a larger select which is supported.
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
+ // X86 wants to expand cmov itself.
+ if (X86DAGIsel) {
+ setOperationAction(ISD::SELECT , MVT::i16 , Custom);
+ setOperationAction(ISD::SELECT , MVT::i32 , Custom);
+ }
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
@@ -930,5 +935,22 @@
Tys.push_back(MVT::Other);
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
}
+ case ISD::SELECT: {
+ unsigned Opc;
+ SDOperand Cond = Op.getOperand(0);
+ SDOperand True = Op.getOperand(1);
+ SDOperand False = Op.getOperand(2);
+ SDOperand CC;
+ if (Cond.getOpcode() == ISD::SETCC) {
+ CC = Cond.getOperand(2);
+ Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
+ Cond.getOperand(0), Cond.getOperand(1));
+ } else {
+ CC = DAG.getCondCode(ISD::SETEQ);
+ Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
+ }
+ return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
+ Op.getOperand(1), Op.getOperand(2), CC, Cond);
+ }
}
}