print instructions through the mcstreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95181 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 7e22b62..674eeb8 100644
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -83,10 +83,6 @@
return "ARM Assembly Printer";
}
- void printMCInst(const MCInst *MI) {
- ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
- }
-
void printInstructionThroughMCStreamer(const MachineInstr *MI);
@@ -1176,7 +1172,7 @@
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
- printMCInst(&AddInst);
+ OutStreamer.EmitInstruction(AddInst);
return;
}
case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
@@ -1217,8 +1213,7 @@
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
- printMCInst(&TmpInst);
- O << '\n';
+ OutStreamer.EmitInstruction(TmpInst);
}
{
@@ -1232,7 +1227,7 @@
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
- printMCInst(&TmpInst);
+ OutStreamer.EmitInstruction(TmpInst);
}
return;
}
@@ -1251,8 +1246,7 @@
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
- printMCInst(&TmpInst);
- O << '\n';
+ OutStreamer.EmitInstruction(TmpInst);
}
{
@@ -1266,7 +1260,7 @@
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
- printMCInst(&TmpInst);
+ OutStreamer.EmitInstruction(TmpInst);
}
return;
@@ -1275,8 +1269,7 @@
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
-
- printMCInst(&TmpInst);
+ OutStreamer.EmitInstruction(TmpInst);
}
//===----------------------------------------------------------------------===//