commit 85509802eba15c82ff486f512a0b559699dc6999
author Eli Friedman <eli.friedman@gmail.com> Tue Sep 24 22:50:14 2013 +0000
committer Eli Friedman <eli.friedman@gmail.com> Tue Sep 24 22:50:14 2013 +0000
tree dde092dacfbbf1fb2f78cbfd5eab7565d616aa16
parent 0c5e6c673098f91fa9d90a15efaadfc767325897

Add missing check to SETCC optimization.

PR17338.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191337 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/TargetLowering.cpp

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index f2199d7..3881b0e 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1185,6 +1185,7 @@
     // the test is for equality or unsigned, and all 1 bits of the const are
     // in the same partial word, see if we can shorten the load.
     if (DCI.isBeforeLegalize() &&
+        !ISD::isSignedIntSetCC(Cond) &&
         N0.getOpcode() == ISD::AND && C1 == 0 &&
         N0.getNode()->hasOneUse() &&
         isa<LoadSDNode>(N0.getOperand(0)) &&