commit 861986401e05e437cb33bfd8320d510b956fe41e
author Evan Cheng <evan.cheng@apple.com> Fri Aug 07 00:34:42 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Aug 07 00:34:42 2009 +0000
tree 69ce77c93aa7b094dd2b99915d40c95b901df17a
parent 3a3cce59c428619513b5209d62f9398b84743cdb

It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index a81b790..ea80e47 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -206,9 +206,13 @@
       if (NewBase == 0)
         return false;
     }
-    int BaseOpc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
+    int BaseOpc = !isThumb2
+      ? ARM::ADDri
+      : ((Base == ARM::SP) ? ARM::t2ADDrSPi : ARM::t2ADDri);
     if (Offset < 0) {
-      BaseOpc = isThumb2 ? ARM::t2SUBri : ARM::SUBri;
+      BaseOpc = !isThumb2
+        ? ARM::SUBri
+        : ((Base == ARM::SP) ? ARM::t2SUBrSPi : ARM::t2SUBri);
       Offset = - Offset;
     }
     int ImmedOffset = isThumb2
@@ -329,6 +333,9 @@
   if (!MI)
     return false;
   if (MI->getOpcode() != ARM::t2SUBri &&
+      MI->getOpcode() != ARM::t2SUBrSPi &&
+      MI->getOpcode() != ARM::t2SUBrSPi12 &&
+      MI->getOpcode() != ARM::tSUBspi &&
       MI->getOpcode() != ARM::SUBri)
     return false;
 
@@ -336,9 +343,10 @@
   if (Bytes <= 0 || (Limit && Bytes >= Limit))
     return false;
 
+  unsigned Scale = (MI->getOpcode() == ARM::tSUBspi) ? 4 : 1; // FIXME
   return (MI->getOperand(0).getReg() == Base &&
           MI->getOperand(1).getReg() == Base &&
-          MI->getOperand(2).getImm() == Bytes &&
+          (MI->getOperand(2).getImm()*Scale) == Bytes &&
           getInstrPredicate(MI, MyPredReg) == Pred &&
           MyPredReg == PredReg);
 }
@@ -350,6 +358,9 @@
   if (!MI)
     return false;
   if (MI->getOpcode() != ARM::t2ADDri &&
+      MI->getOpcode() != ARM::t2ADDrSPi &&
+      MI->getOpcode() != ARM::t2ADDrSPi12 &&
+      MI->getOpcode() != ARM::tADDspi &&
       MI->getOpcode() != ARM::ADDri)
     return false;
 
@@ -357,9 +368,10 @@
     // Make sure the offset fits in 8 bits.
     return false;
 
+  unsigned Scale = (MI->getOpcode() == ARM::tADDspi) ? 4 : 1; // FIXME
   return (MI->getOperand(0).getReg() == Base &&
           MI->getOperand(1).getReg() == Base &&
-          MI->getOperand(2).getImm() == Bytes &&
+          (MI->getOperand(2).getImm()*Scale) == Bytes &&
           getInstrPredicate(MI, MyPredReg) == Pred &&
           MyPredReg == PredReg);
 }