commit 862019c37f5b5d76e34eeb0d5686e617d544059f
author Jim Grosbach <grosbach@apple.com> Tue Oct 18 23:02:30 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Tue Oct 18 23:02:30 2011 +0000
tree 40172dbdd639d490a94121112fdbf2c89ab5fe2f
parent 85f3a0a4c4c1953a06ea463c6b5d6b88d62b58b4

ARM VTBL (one register) assembly parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index ccdac3e..eadd77e 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -990,3 +990,8 @@
                                       raw_ostream &O) {
   O << "[" << MI->getOperand(OpNum).getImm() << "]";
 }
+
+void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
+                                        raw_ostream &O) {
+  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
+}