More working CellSPU tests:
- vec_const.ll: Vector constant loads
- immed64.ll: i64, f64 constant loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45242 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 2ab4841..6b6af64 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -263,10 +263,10 @@
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@@ -441,6 +441,7 @@
LoadSDNode *LN = cast<LoadSDNode>(Op);
SDOperand basep = LN->getBasePtr();
SDOperand the_chain = LN->getChain();
+ MVT::ValueType BasepOpc = basep.Val->getOpcode();
MVT::ValueType VT = LN->getLoadedVT();
MVT::ValueType OpVT = Op.Val->getValueType(0);
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -449,6 +450,11 @@
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
SDOperand Ops[8];
+ if (BasepOpc == ISD::FrameIndex) {
+ // Loading from a frame index is always properly aligned. Always.
+ return SDOperand();
+ }
+
// For an extending load of an i1 variable, just call it i8 (or whatever we
// were passed) and make it zero-extended:
if (VT == MVT::i1) {
@@ -467,11 +473,9 @@
// The vector type we really want to be when we load the 16-byte chunk
MVT::ValueType vecVT, opVecVT;
+ vecVT = MVT::v16i8;
if (VT != MVT::i1)
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
- else
- vecVT = MVT::v16i8;
-
opVecVT = MVT::getVectorType(OpVT, (128 / MVT::getSizeInBits(OpVT)));
if (basep.getOpcode() == ISD::ADD) {
@@ -604,8 +608,8 @@
// address scheme:
SDOperand ZeroOffs = DAG.getConstant(0, PtrVT);
- SDOperand loOp = DAG.getNode(SPUISD::Lo, VT, basep, ZeroOffs);
- SDOperand hiOp = DAG.getNode(SPUISD::Hi, VT, basep, ZeroOffs);
+ SDOperand loOp = DAG.getNode(SPUISD::Lo, PtrVT, basep, ZeroOffs);
+ SDOperand hiOp = DAG.getNode(SPUISD::Hi, PtrVT, basep, ZeroOffs);
ptrp = DAG.getNode(ISD::ADD, PtrVT, loOp, hiOp);