commit 87e369d2217d5932f5c2deff5b3db63f0085dffc
author Misha Brukman <brukman+llvm@gmail.com> Fri Dec 13 12:00:06 2002 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Fri Dec 13 12:00:06 2002 +0000
tree bf2bf3a5c29a98b094b99eab4188f1b368ab200d
parent 74676da6f122bd7abfd2ba47c5291bc9092cee55

Cleaned up the code: factored out switch/case into a separate function, put
constants in an array for quick lookup. Stole the idea from elsewhere in
Jello.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5017 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86RegisterInfo.cpp

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 181cc47..4e5afce 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -23,6 +23,17 @@
   : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0])) {
 }
 
+unsigned getIdx(unsigned dataSize) {
+  switch (dataSize) {
+  case 1: return 0;
+  case 2: return 1;
+  case 4: return 2;
+    // FIXME: longs handled as ints
+  case 8: return 2;
+  default: assert(0 && "Invalid data size!");
+  }
+}
+
 MachineBasicBlock::iterator
 X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator MBBI,
@@ -30,15 +41,8 @@
                                     unsigned ImmOffset, unsigned dataSize)
   const
 {
-  unsigned opcode;
-  switch (dataSize) {
-  case 1: opcode = X86::MOVrm8; break;
-  case 2: opcode = X86::MOVrm16; break;
-  case 4: opcode = X86::MOVrm32; break;
-  default: assert(0 && "Invalid data size!");
-  }
-
-  MachineInstr *MI = addRegOffset(BuildMI(opcode, 5),
+  static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
+  MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(dataSize)], 5),
                                   DestReg, ImmOffset).addReg(SrcReg);
   return ++(MBB->insert(MBBI, MI));
 }
@@ -50,18 +54,9 @@
                                    unsigned ImmOffset, unsigned dataSize)
   const
 {
-  unsigned opcode;
-  switch (dataSize) {
-  case 1: opcode = X86::MOVmr8; break;
-  case 2: opcode = X86::MOVmr16; break;
-  case 4: opcode = X86::MOVmr32; break;
-    // FIXME: longs handled as ints
-  case 8: opcode = X86::MOVmr32; break;
-  default: assert(0 && "Invalid data size!");
-  }
-
-  MachineInstr *MI = addRegOffset(BuildMI(opcode, 5).addReg(DestReg),
-                                  SrcReg, ImmOffset);
+  static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
+  MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(dataSize)], 5)
+                                  .addReg(DestReg), SrcReg, ImmOffset);
   return ++(MBB->insert(MBBI, MI));
 }
 
@@ -71,17 +66,9 @@
                              unsigned DestReg, unsigned SrcReg,
                              unsigned dataSize) const
 {
-  unsigned opcode;
-  switch (dataSize) {
-  case 1: opcode = X86::MOVrr8; break;
-  case 2: opcode = X86::MOVrr16; break;
-  case 4: opcode = X86::MOVrr32; break;
-    // FIXME: longs handled as ints
-  case 8: opcode = X86::MOVrr32; break;
-  default: assert(0 && "Invalid data size!");
-  }
-  
-  MachineInstr *MI = BuildMI(opcode, 2).addReg(DestReg).addReg(SrcReg);
+  static const unsigned Opcode[] = { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
+  MachineInstr *MI = 
+    BuildMI(Opcode[getIdx(dataSize)], 2).addReg(DestReg).addReg(SrcReg);
   return ++(MBB->insert(MBBI, MI));
 }
 
@@ -91,17 +78,9 @@
                              unsigned DestReg, unsigned Imm, unsigned dataSize)
   const
 {
-  unsigned opcode;
-  switch (dataSize) {
-  case 1: opcode = X86::MOVir8; break;
-  case 2: opcode = X86::MOVir16; break;
-  case 4: opcode = X86::MOVir32; break;
-    // FIXME: longs handled as ints
-  case 8: opcode = X86::MOVir32; break;
-  default: assert(0 && "Invalid data size!");
-  }
-  
-  MachineInstr *MI = BuildMI(opcode, 2).addReg(DestReg).addReg(Imm);
+  static const unsigned Opcode[] = { X86::MOVir8, X86::MOVir16, X86::MOVir32 };
+  MachineInstr *MI = 
+    BuildMI(Opcode[getIdx(dataSize)], 2).addReg(DestReg).addReg(Imm);
   return ++(MBB->insert(MBBI, MI));
 }