commit 8a83f71301fdf0e2cea8ecdf413f192ac48ddc5c
author Owen Anderson <resistor@mac.com> Wed Sep 07 21:10:42 2011 +0000
committer Owen Anderson <resistor@mac.com> Wed Sep 07 21:10:42 2011 +0000
tree 86ca1870d5f9bebdbc793f31d0a57bb2ece33181
parent ed1cb6defa02d92302288410c35464c764adb060

Create Thumb2 versions of STC/LDC, and reenable the relevant tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index fa9eed4..13e410c 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -997,6 +997,22 @@
     case ARM::STCL_PRE:
     case ARM::STCL_POST:
     case ARM::STCL_OPTION:
+    case ARM::t2LDC_OFFSET:
+    case ARM::t2LDC_PRE:
+    case ARM::t2LDC_POST:
+    case ARM::t2LDC_OPTION:
+    case ARM::t2LDCL_OFFSET:
+    case ARM::t2LDCL_PRE:
+    case ARM::t2LDCL_POST:
+    case ARM::t2LDCL_OPTION:
+    case ARM::t2STC_OFFSET:
+    case ARM::t2STC_PRE:
+    case ARM::t2STC_POST:
+    case ARM::t2STC_OPTION:
+    case ARM::t2STCL_OFFSET:
+    case ARM::t2STCL_PRE:
+    case ARM::t2STCL_POST:
+    case ARM::t2STCL_OPTION:
       if (coproc == 0xA || coproc == 0xB)
         return MCDisassembler::Fail;
       break;
@@ -1021,6 +1037,12 @@
     case ARM::STCL_POST:
     case ARM::LDC2L_POST:
     case ARM::STC2L_POST:
+    case ARM::t2LDC_OPTION:
+    case ARM::t2LDCL_OPTION:
+    case ARM::t2STC_OPTION:
+    case ARM::t2STCL_OPTION:
+    case ARM::t2LDCL_POST:
+    case ARM::t2STCL_POST:
       break;
     default:
       Inst.addOperand(MCOperand::CreateReg(0));
@@ -1040,6 +1062,8 @@
   switch (Inst.getOpcode()) {
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::t2LDCL_POST:
+    case ARM::t2STCL_POST:
     case ARM::LDC2L_POST:
     case ARM::STC2L_POST:
       imm |= U << 8;
@@ -1051,6 +1075,10 @@
     case ARM::STCL_OPTION:
     case ARM::STC2_OPTION:
     case ARM::STC2L_OPTION:
+    case ARM::t2LDC_OPTION:
+    case ARM::t2LDCL_OPTION:
+    case ARM::t2STC_OPTION:
+    case ARM::t2STCL_OPTION:
       Inst.addOperand(MCOperand::CreateImm(imm));
       break;
     default: