rework the rotate-by-1 instructions to be defined like the
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 37ffeb8..6d4849b 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -771,7 +771,9 @@
// FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
// "shift <op>".
if ((Name.startswith("shr") || Name.startswith("sar") ||
- Name.startswith("shl") || Name.startswith("sal")) &&
+ Name.startswith("shl") || Name.startswith("sal") ||
+ Name.startswith("rcl") || Name.startswith("rcr") ||
+ Name.startswith("rol") || Name.startswith("ror")) &&
Operands.size() == 3) {
X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
@@ -781,14 +783,6 @@
}
}
- // FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
- if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
- Operands.size() == 2) {
- const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
- Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
- std::swap(Operands[1], Operands[2]);
- }
-
// FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
if ((Name.startswith("shld") || Name.startswith("shrd")) &&
Operands.size() == 3) {