Enable element promotion type legalization by deafault.
Changed tests which assumed that vectors are legalized by widening them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
index 8ecf154..f4aad44 100644
--- a/test/CodeGen/CellSPU/shift_ops.ll
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep {shlh } %t1.s | count 10
; RUN: grep {shlhi } %t1.s | count 3
-; RUN: grep {shl } %t1.s | count 11
+; RUN: grep {shl } %t1.s | count 10
; RUN: grep {shli } %t1.s | count 3
; RUN: grep {xshw } %t1.s | count 5
-; RUN: grep {and } %t1.s | count 14
-; RUN: grep {andi } %t1.s | count 2
-; RUN: grep {rotmi } %t1.s | count 2
+; RUN: grep {and } %t1.s | count 15
+; RUN: grep {andi } %t1.s | count 4
+; RUN: grep {rotmi } %t1.s | count 4
; RUN: grep {rotqmbyi } %t1.s | count 1
; RUN: grep {rotqmbii } %t1.s | count 2
; RUN: grep {rotqmby } %t1.s | count 1
diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll
index c88a258..973586b 100644
--- a/test/CodeGen/CellSPU/shuffles.ll
+++ b/test/CodeGen/CellSPU/shuffles.ll
@@ -1,12 +1,14 @@
; RUN: llc -O1 --march=cellspu < %s | FileCheck %s
+;CHECK: shuffle
define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
; CHECK: cwd {{\$.}}, 0($sp)
; CHECK: shufb {{\$., \$4, \$3, \$.}}
%val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> <i32 4,i32 1,i32 2,i32 3>
ret <4 x float> %val
}
-
+
+;CHECK: splat
define <4 x float> @splat(float %param1) {
; CHECK: lqa
; CHECK: shufb $3
@@ -16,6 +18,7 @@
ret <4 x float> %val
}
+;CHECK: test_insert
define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) {
%sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0
;CHECK: lqa $6,
@@ -31,6 +34,7 @@
ret void
}
+;CHECK: test_insert_1
define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
;CHECK: cwd $5, 4($sp)
;CHECK: shufb $3, $4, $3, $5
@@ -39,6 +43,7 @@
ret <4 x float> %rv
}
+;CHECK: test_v2i32
define <2 x i32> @test_v2i32(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 4
@@ -49,17 +54,14 @@
define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
{
-;CHECK: rotqbyi $3, $3, 8
-;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
<4 x i32> <i32 2,i32 3,i32 0, i32 1>
ret <4 x i32> %rv
}
+;CHECK: test_v4i32_rot4
define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
{
-;CHECK: rotqbyi $3, $3, 4
-;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
<4 x i32> <i32 1,i32 2,i32 3, i32 0>
ret <4 x i32> %rv
diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll
index 71d4aba..9c5b896 100644
--- a/test/CodeGen/CellSPU/v2i32.ll
+++ b/test/CodeGen/CellSPU/v2i32.ll
@@ -9,7 +9,8 @@
define %vec @test_add(%vec %param)
{
-;CHECK: a {{\$.}}, $3, $3
+;CHECK: shufb
+;CHECK: addx
%1 = add %vec %param, %param
;CHECK: bi $lr
ret %vec %1
@@ -17,21 +18,14 @@
define %vec @test_sub(%vec %param)
{
-;CHECK: sf {{\$.}}, $4, $3
%1 = sub %vec %param, <i32 1, i32 1>
-
;CHECK: bi $lr
ret %vec %1
}
define %vec @test_mul(%vec %param)
{
-;CHECK: mpyu
-;CHECK: mpyh
-;CHECK: a {{\$., \$., \$.}}
-;CHECK: a {{\$., \$., \$.}}
%1 = mul %vec %param, %param
-
;CHECK: bi $lr
ret %vec %1
}
@@ -56,22 +50,12 @@
define void @test_store( %vec %val, %vec* %ptr)
{
-;CHECK: stqd $3, 0(${{.}})
-;CHECK: bi $lr
store %vec %val, %vec* %ptr
ret void
}
-;Alignment of <2 x i32> is not *directly* defined in the ABI
-;It probably is safe to interpret it as an array, thus having 8 byte
-;alignment (according to ABI). This tests that the size of
-;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the
-;two arrays
define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr)
{
-; CHECK-NOT: ai $3, $3, 16
-; CHECK: ai $3, $3, 8
-; CHECK: bi $lr
%rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1
ret <2 x i32>* %rv
}