commit 9135fcbbab902cc842b73e28fc89e01ae9cd2bcc
author Andrew Lenharth <alenhar2@cs.uiuc.edu> Sat Mar 01 22:27:48 2008 +0000
committer Andrew Lenharth <alenhar2@cs.uiuc.edu> Sat Mar 01 22:27:48 2008 +0000
tree 0f5ef08987bd6e30759e6958267050fdda194bf6
parent 7dfe23f07fa1482f30c658938ea87936c76bbc93

make CAS work

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47799 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 4cb9491..6c7f5fe 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5358,10 +5358,10 @@
   case MVT::i32: Reg = X86::EAX; size = 4; break;
   };
   SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
-                                    Op.getOperand(2), SDOperand());
+                                    Op.getOperand(3), SDOperand());
   SDOperand Ops[] = { cpIn.getValue(0),
                        Op.getOperand(1),
-                       Op.getOperand(3),
+                       Op.getOperand(2),
                        DAG.getTargetConstant(size, MVT::i8),
                        cpIn.getValue(1) };
   SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);