Rename SelectionDAGISel's FastISel to Fast, to begin to make
room for the new FastISel instruction selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54749 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index d1c49d0..815fdb7 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5379,7 +5379,7 @@
if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
- if (!FastISel && EnableValueProp)
+ if (!Fast && EnableValueProp)
ComputeLiveOutVRegInfo(DAG);
// Third, instruction select all of the operations to machine code, adding the
@@ -5448,7 +5448,7 @@
BasicBlock *LLVMBB = &*I;
PHINodesToUpdate.clear();
- if (!FastISel || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB]))
+ if (!Fast || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB]))
SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
}
@@ -5696,7 +5696,7 @@
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
+ ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast);
Scheduler->Run();
return Scheduler;