commit 92ac82abb457354045c0d776e681fa69c589d5e9
author Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 14:21:41 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 14:21:41 2009 +0000
tree bf7bc9bbb867a6e426f115ac21cfa176b94b9570
parent c79465df0848e1784be0f145566f7d4790dbed23

Implement FP regs spills / restores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76024 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZInstrInfo.cpp

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 252a5f6..61f6e93 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -66,6 +66,10 @@
   else if (RC == &SystemZ::GR64RegClass ||
            RC == &SystemZ::ADDR64RegClass) {
     Opc = SystemZ::MOV64mr;
+  } else if (RC == &SystemZ::FP32RegClass) {
+    Opc = SystemZ::FMOV32mr;
+  } else if (RC == &SystemZ::FP64RegClass) {
+    Opc = SystemZ::FMOV64mr;
   } else
     assert(0 && "Unsupported regclass to store");
 
@@ -87,6 +91,10 @@
   else if (RC == &SystemZ::GR64RegClass ||
            RC == &SystemZ::ADDR64RegClass) {
     Opc = SystemZ::MOV64rm;
+  } else if (RC == &SystemZ::FP32RegClass) {
+    Opc = SystemZ::FMOV32rm;
+  } else if (RC == &SystemZ::FP64RegClass) {
+    Opc = SystemZ::FMOV64rm;
   } else
     assert(0 && "Unsupported regclass to store");
 
@@ -369,6 +377,12 @@
   case SystemZ::UCMP32rm:
     Opc = SystemZ::UCMP32rmy;
     break;
+  case SystemZ::FMOV32mr:
+    Opc = SystemZ::FMOV32mry;
+    break;
+  case SystemZ::FMOV64mr:
+    Opc = SystemZ::FMOV64mry;
+    break;
   default:
     break;
   }