Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter.cpp
index b553106..3d8dd75 100644
--- a/lib/CodeGen/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter.cpp
@@ -982,7 +982,7 @@
// Count the number of register definitions.
unsigned NumDefs = 0;
- for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
+ for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef();
++NumDefs)
assert(NumDefs != NumOperands-1 && "No asm string?");
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 3d324b7..e7abd47 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -413,7 +413,7 @@
bool HasUse = mop.isUse();
bool HasDef = mop.isDef();
for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
- if (MI->getOperand(j).isReg() &&
+ if (MI->getOperand(j).isRegister() &&
MI->getOperand(j).getReg() == li.reg) {
MI->getOperand(j).setReg(NewVReg);
HasUse |= MI->getOperand(j).isUse();
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index dd5afcc..57396b7 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -78,7 +78,7 @@
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
+ if (MO.isRegister() && MO.isKill()) {
if ((MO.getReg() == Reg) ||
(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
MRegisterInfo::isPhysicalRegister(Reg) &&
@@ -92,7 +92,7 @@
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
+ if (MO.isRegister() && MO.isDead()) {
if ((MO.getReg() == Reg) ||
(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
MRegisterInfo::isPhysicalRegister(Reg) &&
@@ -106,7 +106,7 @@
bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+ if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return true;
}
return false;
@@ -190,7 +190,7 @@
bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isUse()) {
+ if (MO.isRegister() && MO.isUse()) {
unsigned Reg = MO.getReg();
if (!Reg)
continue;
@@ -221,7 +221,7 @@
bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef()) {
+ if (MO.isRegister() && MO.isDef()) {
unsigned Reg = MO.getReg();
if (!Reg)
continue;
@@ -614,7 +614,7 @@
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
+ if (MO.isRegister() && MO.isKill()) {
MO.unsetIsKill();
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
@@ -630,7 +630,7 @@
void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
+ if (MO.isRegister() && MO.isDead()) {
MO.unsetIsDead();
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index dbf7968..7acd03e 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -66,7 +66,7 @@
assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
- MI->getOperand(2).isImm() && "Malformed extract_subreg");
+ MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
unsigned SuperReg = MI->getOperand(1).getReg();
unsigned SubIdx = MI->getOperand(2).getImm();
@@ -113,7 +113,7 @@
if (MI->getNumOperands() == 3) {
assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
- MI->getOperand(2).isImm() && "Invalid extract_subreg");
+ MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
DstReg = MI->getOperand(0).getReg();
SrcReg = DstReg;
InsReg = MI->getOperand(1).getReg();
@@ -122,7 +122,7 @@
assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
(MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
- MI->getOperand(3).isImm() && "Invalid extract_subreg");
+ MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
DstReg = MI->getOperand(0).getReg();
SrcReg = MI->getOperand(1).getReg();
InsReg = MI->getOperand(2).getReg();
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index d6aab29..1634c78 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -188,7 +188,7 @@
int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
+ if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
if (!isKill || MO.isKill())
return i;
}
@@ -200,7 +200,7 @@
MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+ if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return &MO;
}
return NULL;
@@ -225,7 +225,7 @@
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
+ if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
continue;
for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
MachineOperand &MOp = getOperand(j);
@@ -248,7 +248,7 @@
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
const MachineOperand &MO = MI->getOperand(i);
// Predicated operands must be last operands.
- if (MO.isReg())
+ if (MO.isRegister())
addRegOperand(MO.getReg(), false);
else {
addImmOperand(MO.getImm());
@@ -319,7 +319,7 @@
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
- if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
+ if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
::print(getOperand(0), OS, TM);
if (getOperand(0).isDead())
OS << "<dead>";
@@ -337,7 +337,7 @@
OS << " ";
::print(mop, OS, TM);
- if (mop.isReg()) {
+ if (mop.isRegister()) {
if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
OS << "<";
bool NeedComma = false;
@@ -381,7 +381,7 @@
for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
os << "\t" << getOperand(i);
- if (getOperand(i).isReg() && getOperand(i).isDef())
+ if (getOperand(i).isRegister() && getOperand(i).isDef())
os << "<d>";
}
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index ae40e58..1559212 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -102,7 +102,7 @@
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
@@ -125,7 +125,7 @@
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free.
@@ -155,7 +155,7 @@
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
// Skip two-address destination operand.
if (TID->findTiedToSrcOperand(i) != -1)
@@ -170,7 +170,7 @@
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
@@ -257,7 +257,7 @@
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- if (MO.isReg())
+ if (MO.isRegister())
Candidates.reset(MO.getReg());
}
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 779c36a..5ef838c 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -986,7 +986,7 @@
for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isUse() && MO.getReg() &&
+ if (MO.isRegister() && MO.isUse() && MO.getReg() &&
mri_->regsOverlap(rep(MO.getReg()), Reg)) {
MOU = &MO;
return MI;
@@ -1005,7 +1005,7 @@
MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() &&
+ if (MO.isRegister() && MO.isDef() &&
mri_->regsOverlap(rep(MO.getReg()), Reg))
return &MO;
}
@@ -1017,7 +1017,7 @@
void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill() && MO.getReg() &&
+ if (MO.isRegister() && MO.isKill() && MO.getReg() &&
mri_->regsOverlap(rep(MO.getReg()), Reg))
MO.unsetIsKill();
}
@@ -1041,7 +1041,7 @@
for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill() && MO.getReg() &&
+ if (MO.isRegister() && MO.isKill() && MO.getReg() &&
mri_->regsOverlap(rep(MO.getReg()), Reg)) {
MO.unsetIsKill();
}
@@ -1056,7 +1056,7 @@
bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() &&
+ if (MO.isRegister() && MO.isDef() &&
mri_->regsOverlap(rep(MO.getReg()), Reg))
return true;
}
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 307a8e2..8a1432e 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -446,7 +446,7 @@
SmallVector<unsigned, 1> *KillRegs = NULL) {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
- if (!MO.isReg() || !MO.isUse() || !MO.isKill())
+ if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
continue;
unsigned Reg = MO.getReg();
if (KillRegs)
@@ -471,7 +471,7 @@
MachineOperand *DefOp = NULL;
for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = DefMI->getOperand(i);
- if (MO.isReg() && MO.isDef()) {
+ if (MO.isRegister() && MO.isDef()) {
if (MO.getReg() == Reg)
DefOp = &MO;
else if (!MO.isDead())
@@ -488,7 +488,7 @@
MachineInstr *NMI = I;
for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
MachineOperand &MO = NMI->getOperand(j);
- if (!MO.isReg() || MO.getReg() != Reg)
+ if (!MO.isRegister() || MO.getReg() != Reg)
continue;
if (MO.isUse())
FoundUse = true;
@@ -511,7 +511,7 @@
const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
@@ -535,7 +535,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
RegKills.reset(Reg);
@@ -826,7 +826,7 @@
bool CanReuse = true;
int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
if (ti != -1 &&
- MI.getOperand(ti).isReg() &&
+ MI.getOperand(ti).isRegister() &&
MI.getOperand(ti).getReg() == VirtReg) {
// Okay, we have a two address operand. We can reuse this physreg as
// long as we are allowed to clobber the value and there isn't an