Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll
index c46bcd1..4284c22 100644
--- a/test/CodeGen/CellSPU/loads.ll
+++ b/test/CodeGen/CellSPU/loads.ll
@@ -22,13 +22,15 @@
declare <4 x i32>* @getv4f32ptr()
define <4 x i32> @func() {
- ;CHECK: brasl
- ;CHECK: lr {{\$[0-9]*, \$3}}
- ;CHECK: brasl
- %rv1 = call <4 x i32>* @getv4f32ptr()
- %rv2 = call <4 x i32>* @getv4f32ptr()
- %rv3 = load <4 x i32>* %rv1
- ret <4 x i32> %rv3
+ ;CHECK: brasl
+ ; we need to have some instruction to move the result to safety.
+ ; which instruction (lr, stqd...) depends on the regalloc
+ ;CHECK: {{.*}}
+ ;CHECK: brasl
+ %rv1 = call <4 x i32>* @getv4f32ptr()
+ %rv2 = call <4 x i32>* @getv4f32ptr()
+ %rv3 = load <4 x i32>* %rv1
+ ret <4 x i32> %rv3
}
define <4 x float> @load_undef(){