commit 98b05a57b67d1968381563c8cccbbb6c6cb65e3d
author Jim Grosbach <grosbach@apple.com> Wed Nov 30 01:09:44 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Wed Nov 30 01:09:44 2011 +0000
tree 1f6868b8a57f7b66aca8c50621f1479c52e2a18f
parent 3d925d24e8c54cde05228258c25cc21687cad922

ARM parsing aliases for VLD1 single register all lanes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 6c6c021..ed2594e 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -1029,3 +1029,10 @@
     << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
     << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
 }
+
+void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
+                                                unsigned OpNum,
+                                                raw_ostream &O) {
+  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
+}
+