Replace copyRegToReg with copyPhysReg for Alpha.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108065 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index ab30974..89c2966 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -141,36 +141,25 @@
return 2;
}
-bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC,
- DebugLoc DL) const {
- //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
- if (DestRC != SrcRC) {
- // Not yet supported!
- return false;
- }
-
- if (DestRC == Alpha::GPRCRegisterClass) {
+void AlphaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI, DebugLoc DL,
+ unsigned DestReg, unsigned SrcReg,
+ bool KillSrc) const {
+ if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
.addReg(SrcReg)
- .addReg(SrcReg);
- } else if (DestRC == Alpha::F4RCRegisterClass) {
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
.addReg(SrcReg)
- .addReg(SrcReg);
- } else if (DestRC == Alpha::F8RCRegisterClass) {
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
.addReg(SrcReg)
- .addReg(SrcReg);
+ .addReg(SrcReg, getKillRegState(KillSrc));
} else {
- // Attempt to copy register that is not GPR or FPR
- return false;
+ llvm_unreachable("Attempt to copy register that is not GPR or FPR");
}
-
- return true;
}
void