Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 83a8f80..0d945fd 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2539,8 +2539,8 @@
Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
+ Inst.addOperand(MCOperand::CreateReg(ARM::SP));
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction16(Insn, 3, 4);