| commit | 99fa0a102ae59e2fa489982157dd508cd32caad7 | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Wed Jan 18 09:26:46 2006 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Wed Jan 18 09:26:46 2006 +0000 |
| tree | 048c8855091cae629ca11423db61909dd129a8c4 | |
| parent | 68e5d084f1a51e71b38aceb8ccc12734adcce9ef [diff] [blame] |
SRA shift amount must be in i8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25416 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6a65614..7ed6c94 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1448,7 +1448,7 @@ SDOperand ShOpHi = Op.getOperand(1); SDOperand ShAmt = Op.getOperand(2); SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, - DAG.getConstant(31, MVT::i32)) + DAG.getConstant(31, MVT::i8)) : DAG.getConstant(0, MVT::i32); SDOperand Tmp2, Tmp3;