commit 9d4ed15c9ec97573703247fb4e0d3d8816eb0ef0
author Chris Lattner <sabre@nondot.org> Wed Jan 15 21:14:01 2003 +0000
committer Chris Lattner <sabre@nondot.org> Wed Jan 15 21:14:01 2003 +0000
tree 70fda7e07ef82c32a004106a7aad5124891f398b
parent 0a166155e71910515b79d482e69ac52deb47db06

Adjust to new interfaces


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5314 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAlloc/PhyRegAlloc.cpp

diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 724dbc7..007d075 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -6,8 +6,8 @@
 
 #include "llvm/CodeGen/RegisterAllocation.h"
 #include "RegAllocCommon.h"
+#include "RegClass.h"
 #include "llvm/CodeGen/IGNode.h"
-#include "llvm/CodeGen/RegClass.h"
 #include "llvm/CodeGen/PhyRegAlloc.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineInstrAnnot.h"
@@ -654,7 +654,7 @@
   MachineOperand& Op = MInst->getOperand(OpNum);
   bool isDef =  MInst->operandIsDefined(OpNum);
   bool isDefAndUse =  MInst->operandIsDefinedAndUsed(OpNum);
-  unsigned RegType = MRI.getRegType( LR );
+  unsigned RegType = MRI.getRegType(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
   const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
@@ -888,7 +888,7 @@
       if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
           MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
-          if (MRI.getRegClassIDOfValue(Val) == RC->getID())
+          if (MRI.getRegClassIDOfType(Val->getType()) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
               if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
                 if (LROfVal->hasColor() )