commit 9e071f0ae3eb92c61de4860fdb12d4499b50e392
author Rafael Espindola <rafael.espindola@gmail.com> Mon Oct 02 19:30:56 2006 +0000
committer Rafael Espindola <rafael.espindola@gmail.com> Mon Oct 02 19:30:56 2006 +0000
tree 32825d9a470609b63cd5a3fa7bd2918e9c605fc2
parent 76907e3dafe59fd29d0e5a17263566164904b117

fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index a98064c..e4b591d 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -82,7 +82,11 @@
 
       BR,
 
-      FSITOS
+      FSITOS,
+
+      FSITOD,
+
+      FMRRD
     };
   }
 }
@@ -115,6 +119,8 @@
   case ARMISD::CMP:           return "ARMISD::CMP";
   case ARMISD::BR:            return "ARMISD::BR";
   case ARMISD::FSITOS:        return "ARMISD::FSITOS";
+  case ARMISD::FSITOD:        return "ARMISD::FSITOD";
+  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
   }
 }
 
@@ -237,6 +243,9 @@
 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Copy;
   SDOperand Chain = Op.getOperand(0);
+  SDOperand    R0 = DAG.getRegister(ARM::R0, MVT::i32);
+  SDOperand    R1 = DAG.getRegister(ARM::R1, MVT::i32);
+
   switch(Op.getNumOperands()) {
   default:
     assert(0 && "Do not know how to return this many arguments!");
@@ -248,13 +257,24 @@
   case 3: {
     SDOperand Val = Op.getOperand(1);
     assert(Val.getValueType() == MVT::i32 ||
-	   Val.getValueType() == MVT::f32);
+	   Val.getValueType() == MVT::f32 ||
+	   Val.getValueType() == MVT::f64);
 
-    if (Val.getValueType() == MVT::f32)
-      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
-    Copy = DAG.getCopyToReg(Chain, ARM::R0, Val, SDOperand());
-    if (DAG.getMachineFunction().liveout_empty())
+    if (Val.getValueType() == MVT::f64) {
+      SDVTList    VTs = DAG.getVTList(MVT::Other, MVT::Flag);
+      SDOperand Ops[] = {Chain, R0, R1, Val};
+      Copy  = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+    } else {
+      if (Val.getValueType() == MVT::f32)
+	Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
+      Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand());
+    }
+
+    if (DAG.getMachineFunction().liveout_empty()) {
       DAG.getMachineFunction().addLiveOut(ARM::R0);
+      if (Val.getValueType() == MVT::f64)
+        DAG.getMachineFunction().addLiveOut(ARM::R1);
+    }
     break;
   }
   case 5:
@@ -421,12 +441,15 @@
 }
 
 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
-  SDOperand IntVal = Op.getOperand(0);
+  SDOperand IntVal  = Op.getOperand(0);
   assert(IntVal.getValueType() == MVT::i32);
-  assert(Op.getValueType()     == MVT::f32);
+  MVT::ValueType vt = Op.getValueType();
+  assert(vt == MVT::f32 ||
+         vt == MVT::f64);
 
   SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
-  return  DAG.getNode(ARMISD::FSITOS, MVT::f32, Tmp);
+  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD;
+  return DAG.getNode(op, vt, Tmp);
 }
 
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {