Teach SD some vector identities, allowing us to compile vec_set-9 into:
_test3:
movd %rdi, %xmm1
#IMPLICIT_DEF %xmm0
punpcklqdq %xmm1, %xmm0
ret
instead of:
_test3:
#IMPLICIT_DEF %rax
movd %rax, %xmm0
movd %rdi, %xmm1
punpcklqdq %xmm1, %xmm0
ret
This is still not ideal. There is no reason to two xmm regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48058 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/vec_set-9.ll b/test/CodeGen/X86/vec_set-9.ll
new file mode 100644
index 0000000..d00ceff
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-9.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 1
+
+define <2 x i64> @test3(i64 %A) {
+entry:
+ %B = insertelement <2 x i64> undef, i64 %A, i32 1
+ ret <2 x i64> %B
+}
+