Don't charge the full latency for anti and output dependencies. This is
an area where eventually it would be good to use target-dependent
information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60498 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 73caea9..f3aef57 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -160,9 +160,12 @@
for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
P != PE; ++P) {
SUnit *PredSU = P->Dep;
- unsigned PredLatency = PredSU->CycleBound + PredSU->Latency;
- if (SU->CycleBound < PredLatency) {
- SU->CycleBound = PredLatency;
+ // This assumes that there's no delay for reusing registers.
+ unsigned PredLatency = (P->isCtrl && P->Reg != 0) ? 1 : PredSU->Latency;
+ unsigned PredTotalLatency = PredSU->CycleBound + PredLatency;
+ if (SU->CycleBound < PredTotalLatency ||
+ (SU->CycleBound == PredTotalLatency && !P->isAntiDep)) {
+ SU->CycleBound = PredTotalLatency;
CriticalPath[*I] = &*P;
}
}