Now that we know if we had a total fail on the instruction mnemonic,
give a more detailed error. Before:
t.s:11:4: error: unrecognized instruction
addl $1, $1
^
t.s:12:4: error: unrecognized instruction
f2efqefa $1
^
After:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
f2efqefa $1
^
This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113176 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 52ca15b..20ed232 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -862,6 +862,8 @@
MCInst &Inst) {
assert(!Operands.empty() && "Unexpect empty operand list!");
+ bool WasOriginallyInvalidOperand = false;
+
// First, try a direct match.
switch (MatchInstructionImpl(Operands, Inst)) {
case Match_Success:
@@ -869,7 +871,10 @@
case Match_MissingFeature:
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
- default:
+ case Match_InvalidOperand:
+ WasOriginallyInvalidOperand = true;
+ break;
+ case Match_MnemonicFail:
break;
}
@@ -941,23 +946,38 @@
return true;
}
- unsigned NumMatchFailures =
- (MatchB == Match_Fail) + (MatchW == Match_Fail) +
- (MatchL == Match_Fail) + (MatchQ == Match_Fail);
+ // Okay, we know that none of the variants matched successfully.
+ // If all of the instructions reported an invalid mnemonic, then the original
+ // mnemonic was invalid.
+ if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) &&
+ (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) {
+ if (WasOriginallyInvalidOperand)
+ Error(IDLoc, "invalid operand for instruction");
+ else
+ Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
+ return true;
+ }
// If one instruction matched with a missing feature, report this as a
// missing feature.
if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) +
- (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1&&
- NumMatchFailures == 3) {
+ (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
}
+ // If one instruction matched with an invalid operand, report this as an
+ // operand failure.
+ if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) +
+ (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){
+ Error(IDLoc, "invalid operand for instruction");
+ return true;
+ }
+
// If all of these were an outright failure, report it in a useless way.
// FIXME: We should give nicer diagnostics about the exact failure.
- Error(IDLoc, "unrecognized instruction");
+ Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
return true;
}