Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67335 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 35c069a..3b923ef 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -234,7 +234,7 @@
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
MachineOperand &MO = UseMI->getOperand(i);
if (MO.isReg() && MO.getReg() == Reg &&
- (MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1))
+ (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
// Earlier use is a two-address one.
return true;
}
@@ -338,8 +338,8 @@
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
continue;
- int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
- if (ti != -1) {
+ unsigned ti;
+ if (MI.isRegTiedToDefOperand(i, &ti)) {
DstReg = MI.getOperand(ti).getReg();
return true;
}
@@ -635,8 +635,8 @@
ProcessCopy(&*mi, &*mbbi, Processed);
for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
- int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
- if (ti == -1)
+ unsigned ti = 0;
+ if (!mi->isRegTiedToDefOperand(si, &ti))
continue;
if (FirstTied) {
@@ -669,7 +669,7 @@
// b + a for example) because our transformation will not work. This
// should never occur because we are in SSA form.
for (unsigned i = 0; i != mi->getNumOperands(); ++i)
- assert((int)i == ti ||
+ assert(i == ti ||
!mi->getOperand(i).isReg() ||
mi->getOperand(i).getReg() != regA);
#endif