Change the informal convention of DBG_VALUE so that we can express a
register-indirect address with an offset of 0.
It used to be that a DBG_VALUE is a register-indirect value if the offset
(operand 1) is nonzero. The new convention is that a DBG_VALUE is
register-indirect if the first operand is a register and the second
operand is an immediate. For plain registers use the combination reg, reg.
rdar://problem/13658587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180816 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 4a71ad3..284b616 100644
--- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -597,7 +597,9 @@
OS << AP.TM.getRegisterInfo()->getName(MI->getOperand(0).getReg());
}
- OS << '+' << MI->getOperand(1).getImm();
+ // It's only an offset if it's an immediate.
+ if (MI->getOperand(1).isImm())
+ OS << '+' << MI->getOperand(1).getImm();
// NOTE: Want this comment at start of line, don't emit with AddComment.
AP.OutStreamer.EmitRawText(OS.str());
return true;
diff --git a/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index ee6308c..b8959ad 100644
--- a/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -1115,7 +1115,8 @@
assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
return MI->getNumOperands() == 3 &&
MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&
- MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;
+ (MI->getOperand(1).isImm() ||
+ (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == 0U));
}
// Get .debug_loc entry for the instruction range starting at MI.
@@ -1129,12 +1130,11 @@
MachineLocation MLoc = Asm->getDebugValueLocation(MI);
return DotDebugLocEntry(FLabel, SLabel, MLoc, Var);
}
- if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {
+ if (MI->getOperand(0).isReg()) {
MachineLocation MLoc;
- // TODO: Currently an offset of 0 in a DBG_VALUE means
- // we need to generate a direct register value.
- // There is no way to specify an indirect value with offset 0.
- if (MI->getOperand(1).getImm() == 0)
+ // If the second operand is an immediate, this is a
+ // register-indirect address.
+ if (!MI->getOperand(1).isImm())
MLoc.set(MI->getOperand(0).getReg());
else
MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
diff --git a/lib/CodeGen/LiveDebugVariables.cpp b/lib/CodeGen/LiveDebugVariables.cpp
index 0b117ac..d54a013 100644
--- a/lib/CodeGen/LiveDebugVariables.cpp
+++ b/lib/CodeGen/LiveDebugVariables.cpp
@@ -108,6 +108,7 @@
class UserValue {
const MDNode *variable; ///< The debug info variable we are part of.
unsigned offset; ///< Byte offset into variable.
+ bool Indirect; ///< true if this is a register-indirect+offset value.
DebugLoc dl; ///< The debug location for the variable. This is
///< used by dwarf writer to find lexical scope.
UserValue *leader; ///< Equivalence class leader.
@@ -134,9 +135,10 @@
public:
/// UserValue - Create a new UserValue.
- UserValue(const MDNode *var, unsigned o, DebugLoc L,
+ UserValue(const MDNode *var, unsigned o, bool i, DebugLoc L,
LocMap::Allocator &alloc)
- : variable(var), offset(o), dl(L), leader(this), next(0), locInts(alloc)
+ : variable(var), offset(o), Indirect(i), dl(L), leader(this),
+ next(0), locInts(alloc)
{}
/// getLeader - Get the leader of this value's equivalence class.
@@ -299,7 +301,8 @@
UVMap userVarMap;
/// getUserValue - Find or create a UserValue.
- UserValue *getUserValue(const MDNode *Var, unsigned Offset, DebugLoc DL);
+ UserValue *getUserValue(const MDNode *Var, unsigned Offset,
+ bool Indirect, DebugLoc DL);
/// lookupVirtReg - Find the EC leader for VirtReg or null.
UserValue *lookupVirtReg(unsigned VirtReg);
@@ -414,7 +417,7 @@
}
UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset,
- DebugLoc DL) {
+ bool Indirect, DebugLoc DL) {
UserValue *&Leader = userVarMap[Var];
if (Leader) {
UserValue *UV = Leader->getLeader();
@@ -424,7 +427,7 @@
return UV;
}
- UserValue *UV = new UserValue(Var, Offset, DL, allocator);
+ UserValue *UV = new UserValue(Var, Offset, Indirect, DL, allocator);
userValues.push_back(UV);
Leader = UserValue::merge(Leader, UV);
return UV;
@@ -445,15 +448,17 @@
bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
// DBG_VALUE loc, offset, variable
if (MI->getNumOperands() != 3 ||
- !MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
+ !(MI->getOperand(1).isReg() || MI->getOperand(1).isImm()) ||
+ !MI->getOperand(2).isMetadata()) {
DEBUG(dbgs() << "Can't handle " << *MI);
return false;
}
// Get or create the UserValue for (variable,offset).
- unsigned Offset = MI->getOperand(1).getImm();
+ bool Indirect = MI->getOperand(1).isImm();
+ unsigned Offset = Indirect ? MI->getOperand(1).getImm() : 0;
const MDNode *Var = MI->getOperand(2).getMetadata();
- UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc());
+ UserValue *UV = getUserValue(Var, Offset, Indirect, MI->getDebugLoc());
UV->addDef(Idx, MI->getOperand(0));
return true;
}
@@ -924,7 +929,8 @@
// Frame index locations may require a target callback.
if (Loc.isFI()) {
MachineInstr *MI = TII.emitFrameIndexDebugValue(*MBB->getParent(),
- Loc.getIndex(), offset, variable,
+ Loc.getIndex(),
+ offset, variable,
findDebugLoc());
if (MI) {
MBB->insert(I, MI);
@@ -932,8 +938,13 @@
}
}
// This is not a frame index, or the target is happy with a standard FI.
- BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
- .addOperand(Loc).addImm(offset).addMetadata(variable);
+
+ if (Loc.isReg())
+ BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
+ Indirect, Loc.getReg(), offset, variable);
+ else
+ BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
+ .addOperand(Loc).addImm(offset).addMetadata(variable);
}
void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 288499a..df2017d 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -641,11 +641,11 @@
Reg = FuncInfo.InitializeRegForValue(Address);
if (Reg)
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- TII.get(TargetOpcode::DBG_VALUE))
- .addReg(Reg, RegState::Debug).addImm(Offset)
- .addMetadata(DI->getVariable());
- else
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(TargetOpcode::DBG_VALUE),
+ DI->getAddress()->getType()->isPointerTy(),
+ Reg, Offset, DI->getVariable());
+ else
// We can't yet handle anything else here because it would require
// generating code, thus altering codegen because of debug info.
DEBUG(dbgs() << "Dropping debug info for " << DI);
@@ -676,9 +676,8 @@
.addFPImm(CF).addImm(DI->getOffset())
.addMetadata(DI->getVariable());
} else if (unsigned Reg = lookUpRegForValue(V)) {
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
- .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
- .addMetadata(DI->getVariable());
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, DI->getOffset() != 0,
+ Reg, DI->getOffset(), DI->getVariable());
} else {
// We can't yet handle anything else here because it would require
// generating code, thus altering codegen because of debug info.
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 3b1abd7..060492e 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -678,7 +678,13 @@
MIB.addReg(0U);
}
- MIB.addImm(Offset).addMetadata(MDPtr);
+ if (Offset != 0) // Indirect addressing.
+ MIB.addImm(Offset);
+ else
+ MIB.addReg(0U, RegState::Debug);
+
+ MIB.addMetadata(MDPtr);
+
return &*MIB;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 6e613d6..eff4c21 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4413,8 +4413,9 @@
return false;
MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
- TII->get(TargetOpcode::DBG_VALUE))
- .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
+ TII->get(TargetOpcode::DBG_VALUE),
+ Offset != 0,
+ Reg, Offset, Variable);
FuncInfo.ArgDbgValues.push_back(&*MIB);
return true;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index e21f26e..806e464 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -418,12 +418,14 @@
MachineBasicBlock::iterator InsertPos = Def;
const MDNode *Variable =
MI->getOperand(MI->getNumOperands()-1).getMetadata();
- unsigned Offset = MI->getOperand(1).getImm();
+ unsigned Offset = 0;
+ if (MI->getOperand(1).isImm())
+ Offset = MI->getOperand(1).getImm();
// Def is never a terminator here, so it is ok to increment InsertPos.
BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
- TII.get(TargetOpcode::DBG_VALUE))
- .addReg(LDI->second, RegState::Debug)
- .addImm(Offset).addMetadata(Variable);
+ TII.get(TargetOpcode::DBG_VALUE),
+ MI->getOperand(1).isReg(),
+ LDI->second, Offset, Variable);
// If this vreg is directly copied into an exported register then
// that COPY instructions also need DBG_VALUE, if it is the only
@@ -442,9 +444,10 @@
if (CopyUseMI) {
MachineInstr *NewMI =
BuildMI(*MF, CopyUseMI->getDebugLoc(),
- TII.get(TargetOpcode::DBG_VALUE))
- .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
- .addImm(Offset).addMetadata(Variable);
+ TII.get(TargetOpcode::DBG_VALUE),
+ Offset!=0,
+ CopyUseMI->getOperand(0).getReg(),
+ Offset, Variable);
MachineBasicBlock::iterator Pos = CopyUseMI;
EntryMBB->insertAfter(Pos, NewMI);
}