Add assertions to the trivial scheduler to check that the value types match
up between defs and uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23590 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index ca01486..3a75d07 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -1102,6 +1102,20 @@
unsigned VReg = EmitDAG(Op.getOperand(i));
MI->addRegOperand(VReg, MachineOperand::Use);
+
+ // Verify that it is right.
+ assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+ assert(II.OpInfo[i+NumResults].RegClass &&
+ "Don't have operand info for this instruction!");
+#ifndef NDEBUG
+ if (RegMap->getRegClass(VReg) != II.OpInfo[i+NumResults].RegClass) {
+ std::cerr << "OP: ";
+ Op.getOperand(i).Val->dump(&DAG); std::cerr << "\nUSE: ";
+ Op.Val->dump(&DAG); std::cerr << "\n";
+ }
+#endif
+ assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
+ "Register class of operand and regclass of use don't agree!");
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
MI->addZeroExtImm64Operand(C->getValue());
@@ -1129,6 +1143,13 @@
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = EmitDAG(Op.getOperand(i));
MI->addRegOperand(VReg, MachineOperand::Use);
+
+ // Verify that it is right.
+ assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+ assert(II.OpInfo[i+NumResults].RegClass &&
+ "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
+ "Register class of operand and regclass of use don't agree!");
}
}