commit a59d469e9b31087f0f045bcb5d1a154c963be9b7
author Scott Michel <scottm@aero.org> Sat Feb 23 18:41:37 2008 +0000
committer Scott Michel <scottm@aero.org> Sat Feb 23 18:41:37 2008 +0000
tree 69a653dae42a34dea6cb63148ac5c417ea1c3a65
parent f65a0f7860bc9189c95a76cb6802d7ba54e61048

Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 64f6225..5eb467e 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -49,14 +49,13 @@
     break;
   case SPU::ORIv4i32:
   case SPU::ORIr32:
-  case SPU::ORIr64:
   case SPU::ORHIv8i16:
   case SPU::ORHIr16:
-  case SPU::ORHI1To2:
+  case SPU::ORHIi8i16:
   case SPU::ORBIv16i8:
   case SPU::ORBIr8:
-  case SPU::ORI2To4:
-  case SPU::ORI1To4:
+  case SPU::ORIi16i32:
+  case SPU::ORIi8i32:
   case SPU::AHIvec:
   case SPU::AHIr16:
   case SPU::AIvec:
@@ -103,7 +102,6 @@
   case SPU::ORr64:
   case SPU::ORf32:
   case SPU::ORf64:
-  case SPU::ORgprc:
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
@@ -203,14 +201,15 @@
     BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
   } else if (DestRC == SPU::R64CRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
+    BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
+      .addReg(SrcReg);
   } else if (DestRC == SPU::R64FPRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
-  } else if (DestRC == SPU::GPRCRegisterClass) {
+  } /* else if (DestRC == SPU::GPRCRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
-  } else if (DestRC == SPU::VECREGRegisterClass) {
+  } */ else if (DestRC == SPU::VECREGRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
   } else {