Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 662ab01..ad8ba6c 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -76,12 +77,15 @@
namespace {
class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
+ AliasAnalysis *AA;
+
public:
static char ID;
PostRAScheduler() : MachineFunctionPass(&ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
+ AU.addRequired<AliasAnalysis>();
AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>();
@@ -119,6 +123,9 @@
/// HazardRec - The hazard recognizer to use.
ScheduleHazardRecognizer *HazardRec;
+ /// AA - AliasAnalysis for making memory reference queries.
+ AliasAnalysis *AA;
+
/// Classes - For live regs that are only used in one register class in a
/// live range, the register class. If the register is not live, the
/// corresponding value is null. If the register is live but used in
@@ -146,10 +153,11 @@
SchedulePostRATDList(MachineFunction &MF,
const MachineLoopInfo &MLI,
const MachineDominatorTree &MDT,
- ScheduleHazardRecognizer *HR)
+ ScheduleHazardRecognizer *HR,
+ AliasAnalysis *aa)
: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
AllocatableSet(TRI->getAllocatableSet(MF)),
- HazardRec(HR) {}
+ HazardRec(HR), AA(aa) {}
~SchedulePostRATDList() {
delete HazardRec;
@@ -241,7 +249,7 @@
(ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
- SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
+ SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA);
// Loop over all of the basic blocks
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
@@ -379,7 +387,7 @@
DEBUG(errs() << "********** List Scheduling **********\n");
// Build the scheduling graph.
- BuildSchedGraph();
+ BuildSchedGraph(AA);
if (EnableAntiDepBreaking) {
if (BreakAntiDependencies()) {
@@ -392,7 +400,7 @@
SUnits.clear();
EntrySU = SUnit();
ExitSU = SUnit();
- BuildSchedGraph();
+ BuildSchedGraph(AA);
}
}